Lines Matching refs:REG_WRITE
134 REG_WRITE(dspcntr_reg, dspcntr); in mdfld__intel_plane_set_alpha()
192 REG_WRITE(map->stride, fb->pitches[0]); in mdfld__intel_pipe_set_base()
211 REG_WRITE(map->cntr, dspcntr); in mdfld__intel_pipe_set_base()
215 REG_WRITE(map->linoff, offset); in mdfld__intel_pipe_set_base()
217 REG_WRITE(map->surf, start); in mdfld__intel_pipe_set_base()
245 REG_WRITE(map->cntr, in mdfld_disable_crtc()
248 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_disable_crtc()
259 REG_WRITE(map->conf, temp); in mdfld_disable_crtc()
272 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
280 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
329 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
334 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
339 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
357 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
360 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
366 REG_WRITE(map->conf, pipeconf); in mdfld_crtc_dpms()
375 REG_WRITE(map->status, REG_READ(map->status)); in mdfld_crtc_dpms()
383 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
385 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
387 REG_WRITE(0xb048, 1); in mdfld_crtc_dpms()
391 REG_WRITE(map->conf, temp); in mdfld_crtc_dpms()
393 REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 0); in mdfld_crtc_dpms()
395 REG_WRITE(0xb004, REG_READ(0xb004)); in mdfld_crtc_dpms()
397 REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 1); in mdfld_crtc_dpms()
399 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
401 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
403 REG_WRITE(0xb048, 2); in mdfld_crtc_dpms()
407 REG_WRITE(map->conf, temp); in mdfld_crtc_dpms()
428 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); in mdfld_crtc_dpms()
433 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
436 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
445 REG_WRITE(map->conf, temp); in mdfld_crtc_dpms()
458 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
753 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); in mdfld_crtc_mode_set()
757 REG_WRITE(PFIT_CONTROL, 0); in mdfld_crtc_mode_set()
774 REG_WRITE(map->size, ((min(mode->crtc_vdisplay, adjusted_mode->crtc_vdisplay) - 1) << 16) in mdfld_crtc_mode_set()
777 REG_WRITE(map->src, ((mode->crtc_hdisplay - 1) << 16) in mdfld_crtc_mode_set()
780 REG_WRITE(map->size, in mdfld_crtc_mode_set()
783 REG_WRITE(map->src, in mdfld_crtc_mode_set()
788 REG_WRITE(map->pos, 0); in mdfld_crtc_mode_set()
806 REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) | in mdfld_crtc_mode_set()
808 REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) | in mdfld_crtc_mode_set()
810 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - in mdfld_crtc_mode_set()
813 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - in mdfld_crtc_mode_set()
816 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - in mdfld_crtc_mode_set()
819 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - in mdfld_crtc_mode_set()
823 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in mdfld_crtc_mode_set()
825 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in mdfld_crtc_mode_set()
827 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in mdfld_crtc_mode_set()
829 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in mdfld_crtc_mode_set()
831 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in mdfld_crtc_mode_set()
833 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in mdfld_crtc_mode_set()
919 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
927 REG_WRITE(map->fp0, 0); in mdfld_crtc_mode_set()
929 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
938 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
979 REG_WRITE(map->fp0, fp); in mdfld_crtc_mode_set()
980 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
985 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
1000 REG_WRITE(map->conf, dev_priv->pipeconf[pipe]); in mdfld_crtc_mode_set()
1004 REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]); in mdfld_crtc_mode_set()