81 	u32 hdisplay;  member
408 	writel((DPE_HEIGHT(mode->vdisplay) << 16) | DPE_WIDTH(mode->hdisplay),  in dpe_dpp_init()
410 	writel((DPE_HEIGHT(mode->vdisplay) << 16) | DPE_WIDTH(mode->hdisplay),  in dpe_dpp_init()
505 	hfp = mode->hsync_start - mode->hdisplay;  in dpe_dbuf_init()
514 	if (mode->hdisplay * mode->vdisplay >= RES_4K_PHONE)  in dpe_dbuf_init()
521 	thd_cg_out = (DFS_TIME * adj_mode->clock * 1000UL * mode->hdisplay) /  in dpe_dbuf_init()
522 		(((hsw + hbp + hfp) + mode->hdisplay) * 6 * 1000000UL);  in dpe_dbuf_init()
533 	sram_min_support_depth = dfs_time_min * mode->hdisplay /  in dpe_dbuf_init()
542 	writel(mode->hdisplay * mode->vdisplay, dbuf_base + DBUF_FRM_SIZE);  in dpe_dbuf_init()
543 	writel(DPE_WIDTH(mode->hdisplay), dbuf_base + DBUF_FRM_HSIZE);  in dpe_dbuf_init()
572 	hfp = mode->hsync_start - mode->hdisplay;  in dpe_ldi_init()
581 	rect.x2 = mode->hdisplay;  in dpe_ldi_init()
619 	dpe_ovl_init(ctx, mode->hdisplay, mode->vdisplay);  in dpe_init()
624 	ctx->hdisplay = mode->hdisplay;  in dpe_init()
954 	dpe_ovl_config(ctx, &rect, ctx->hdisplay, ctx->vdisplay);  in dpe_update_channel()
1020 	if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay ||  in dpe_plane_atomic_check()