1492 	int link_clock;  in icl_ddi_clock_get()  local
1495 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);  in icl_ddi_clock_get()
1501 			link_clock = icl_calc_tbt_pll_link(dev_priv, port);  in icl_ddi_clock_get()
1503 			link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);  in icl_ddi_clock_get()
1506 	pipe_config->port_clock = link_clock;  in icl_ddi_clock_get()
1516 	int link_clock;  in cnl_ddi_clock_get()  local
1519 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);  in cnl_ddi_clock_get()
1521 		link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;  in cnl_ddi_clock_get()
1523 		switch (link_clock) {  in cnl_ddi_clock_get()
1525 			link_clock = 81000;  in cnl_ddi_clock_get()
1528 			link_clock = 108000;  in cnl_ddi_clock_get()
1531 			link_clock = 135000;  in cnl_ddi_clock_get()
1534 			link_clock = 162000;  in cnl_ddi_clock_get()
1537 			link_clock = 216000;  in cnl_ddi_clock_get()
1540 			link_clock = 270000;  in cnl_ddi_clock_get()
1543 			link_clock = 324000;  in cnl_ddi_clock_get()
1546 			link_clock = 405000;  in cnl_ddi_clock_get()
1552 		link_clock *= 2;  in cnl_ddi_clock_get()
1555 	pipe_config->port_clock = link_clock;  in cnl_ddi_clock_get()
1564 	int link_clock;  in skl_ddi_clock_get()  local
1571 		link_clock = skl_calc_wrpll_link(pll_state);  in skl_ddi_clock_get()
1573 		link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);  in skl_ddi_clock_get()
1574 		link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);  in skl_ddi_clock_get()
1576 		switch (link_clock) {  in skl_ddi_clock_get()
1578 			link_clock = 81000;  in skl_ddi_clock_get()
1581 			link_clock = 108000;  in skl_ddi_clock_get()
1584 			link_clock = 135000;  in skl_ddi_clock_get()
1587 			link_clock = 162000;  in skl_ddi_clock_get()
1590 			link_clock = 216000;  in skl_ddi_clock_get()
1593 			link_clock = 270000;  in skl_ddi_clock_get()
1599 		link_clock *= 2;  in skl_ddi_clock_get()
1602 	pipe_config->port_clock = link_clock;  in skl_ddi_clock_get()
1611 	int link_clock = 0;  in hsw_ddi_clock_get()  local
1617 		link_clock = 81000;  in hsw_ddi_clock_get()
1620 		link_clock = 135000;  in hsw_ddi_clock_get()
1623 		link_clock = 270000;  in hsw_ddi_clock_get()
1626 		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));  in hsw_ddi_clock_get()
1629 		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));  in hsw_ddi_clock_get()
1634 			link_clock = 81000;  in hsw_ddi_clock_get()
1636 			link_clock = 135000;  in hsw_ddi_clock_get()
1638 			link_clock = 270000;  in hsw_ddi_clock_get()
1649 	pipe_config->port_clock = link_clock * 2;  in hsw_ddi_clock_get()
2582 					   int link_clock,  in icl_mg_phy_ddi_vswing_sequence()  argument
2658 		if (link_clock < 300000)  in icl_mg_phy_ddi_vswing_sequence()
2669 		if (link_clock <= 500000) {  in icl_mg_phy_ddi_vswing_sequence()
2679 		if (link_clock <= 500000) {  in icl_mg_phy_ddi_vswing_sequence()
2701 				    int link_clock,  in icl_ddi_vswing_sequence()  argument
2711 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);  in icl_ddi_vswing_sequence()