Lines Matching refs:dpll_hw_state
1381 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1400 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1403 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1431 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1449 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1460 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1462 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; in chv_enable_pll()
1470 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1488 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll()
1511 crtc_state->dpll_hw_state.dpll_md); in i9xx_enable_pll()
6913 I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
6914 I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
7580 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
7584 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
7586 crtc_state->dpll_hw_state.fp1 = fp; in i9xx_update_pll_dividers()
7707 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
7710 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
7714 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
7717 pipe_config->dpll_hw_state.dpll_md = in vlv_compute_dpll()
7724 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
7727 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
7731 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
7733 pipe_config->dpll_hw_state.dpll_md = in chv_compute_dpll()
7749 pipe_config->dpll_hw_state.dpll & in vlv_prepare_pll()
7753 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
7851 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
7854 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
8061 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
8066 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
8117 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
8346 memset(&crtc_state->dpll_hw_state, 0, in i8xx_crtc_compute_clock()
8347 sizeof(crtc_state->dpll_hw_state)); in i8xx_crtc_compute_clock()
8381 memset(&crtc_state->dpll_hw_state, 0, in g4x_crtc_compute_clock()
8382 sizeof(crtc_state->dpll_hw_state)); in g4x_crtc_compute_clock()
8424 memset(&crtc_state->dpll_hw_state, 0, in pnv_crtc_compute_clock()
8425 sizeof(crtc_state->dpll_hw_state)); in pnv_crtc_compute_clock()
8458 memset(&crtc_state->dpll_hw_state, 0, in i9xx_crtc_compute_clock()
8459 sizeof(crtc_state->dpll_hw_state)); in i9xx_crtc_compute_clock()
8490 memset(&crtc_state->dpll_hw_state, 0, in chv_crtc_compute_clock()
8491 sizeof(crtc_state->dpll_hw_state)); in chv_crtc_compute_clock()
8511 memset(&crtc_state->dpll_hw_state, 0, in vlv_crtc_compute_clock()
8512 sizeof(crtc_state->dpll_hw_state)); in vlv_crtc_compute_clock()
8572 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
8683 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
8837 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
8850 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8852 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
8853 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
8856 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
9628 crtc_state->dpll_hw_state.dpll = dpll; in ironlake_compute_dpll()
9629 crtc_state->dpll_hw_state.fp0 = fp; in ironlake_compute_dpll()
9630 crtc_state->dpll_hw_state.fp1 = fp2; in ironlake_compute_dpll()
9642 memset(&crtc_state->dpll_hw_state, 0, in ironlake_crtc_compute_clock()
9643 sizeof(crtc_state->dpll_hw_state)); in ironlake_crtc_compute_clock()
10025 &pipe_config->dpll_hw_state)); in ironlake_get_pipe_config()
10027 tmp = pipe_config->dpll_hw_state.dpll; in ironlake_get_pipe_config()
10380 &pipe_config->dpll_hw_state)); in haswell_get_ddi_port_state()
11271 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk()
11290 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get()
11297 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
11299 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
12160 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); in intel_dump_pipe_config()
12256 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; in clear_intel_crtc_state()
12795 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); in intel_pipe_config_compare()
12796 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); in intel_pipe_config_compare()
12797 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); in intel_pipe_config_compare()
12798 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); in intel_pipe_config_compare()
12799 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); in intel_pipe_config_compare()
12800 PIPE_CONF_CHECK_X(dpll_hw_state.spll); in intel_pipe_config_compare()
12801 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); in intel_pipe_config_compare()
12802 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); in intel_pipe_config_compare()
12803 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); in intel_pipe_config_compare()
12804 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()
12805 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); in intel_pipe_config_compare()
12806 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); in intel_pipe_config_compare()
12807 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); in intel_pipe_config_compare()
12808 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); in intel_pipe_config_compare()
12809 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); in intel_pipe_config_compare()
12810 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); in intel_pipe_config_compare()
12811 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); in intel_pipe_config_compare()
12812 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); in intel_pipe_config_compare()
12813 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); in intel_pipe_config_compare()
12814 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); in intel_pipe_config_compare()
12815 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); in intel_pipe_config_compare()
12816 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); in intel_pipe_config_compare()
12817 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); in intel_pipe_config_compare()
12818 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); in intel_pipe_config_compare()
12819 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); in intel_pipe_config_compare()
12820 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); in intel_pipe_config_compare()
12821 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); in intel_pipe_config_compare()
12822 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); in intel_pipe_config_compare()
12823 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); in intel_pipe_config_compare()
12824 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); in intel_pipe_config_compare()
12825 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); in intel_pipe_config_compare()
13173 struct intel_dpll_hw_state dpll_hw_state; in verify_single_dpll_state() local
13177 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); in verify_single_dpll_state()
13181 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state); in verify_single_dpll_state()
13217 &dpll_hw_state, in verify_single_dpll_state()
13218 sizeof(dpll_hw_state)), in verify_single_dpll_state()