Lines Matching refs:pipe_config
1728 struct intel_crtc_state *pipe_config) in intel_dp_set_clock() argument
1750 if (pipe_config->port_clock == divisor[i].clock) { in intel_dp_set_clock()
1751 pipe_config->dpll = divisor[i].dpll; in intel_dp_set_clock()
1752 pipe_config->clock_set = true; in intel_dp_set_clock()
1833 const struct intel_crtc_state *pipe_config) in intel_dp_source_supports_fec() argument
1838 pipe_config->cpu_transcoder != TRANSCODER_A; in intel_dp_source_supports_fec()
1842 const struct intel_crtc_state *pipe_config) in intel_dp_supports_fec() argument
1844 return intel_dp_source_supports_fec(intel_dp, pipe_config) && in intel_dp_supports_fec()
1849 const struct intel_crtc_state *pipe_config) in intel_dp_source_supports_dsc() argument
1854 pipe_config->cpu_transcoder != TRANSCODER_A; in intel_dp_source_supports_dsc()
1858 const struct intel_crtc_state *pipe_config) in intel_dp_supports_dsc() argument
1860 if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable) in intel_dp_supports_dsc()
1863 return intel_dp_source_supports_dsc(intel_dp, pipe_config) && in intel_dp_supports_dsc()
1868 struct intel_crtc_state *pipe_config) in intel_dp_compute_bpp() argument
1874 bpp = pipe_config->pipe_bpp; in intel_dp_compute_bpp()
1896 struct intel_crtc_state *pipe_config, in intel_dp_adjust_compliance_config() argument
1904 pipe_config->dither_force_disable = bpp == 6 * 3; in intel_dp_adjust_compliance_config()
1945 struct intel_crtc_state *pipe_config, in intel_dp_compute_link_config_wide() argument
1948 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_compute_link_config_wide()
1953 int output_bpp = intel_dp_output_bpp(pipe_config, bpp); in intel_dp_compute_link_config_wide()
1967 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide()
1968 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
1969 pipe_config->port_clock = link_clock; in intel_dp_compute_link_config_wide()
1996 struct intel_crtc_state *pipe_config, in intel_dp_dsc_compute_config() argument
2002 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_dsc_compute_config()
2007 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && in intel_dp_dsc_compute_config()
2008 intel_dp_supports_fec(intel_dp, pipe_config); in intel_dp_dsc_compute_config()
2010 if (!intel_dp_supports_dsc(intel_dp, pipe_config)) in intel_dp_dsc_compute_config()
2027 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_config()
2028 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; in intel_dp_dsc_compute_config()
2029 pipe_config->lane_count = limits->max_lane_count; in intel_dp_dsc_compute_config()
2032 pipe_config->dsc_params.compressed_bpp = in intel_dp_dsc_compute_config()
2034 pipe_config->pipe_bpp); in intel_dp_dsc_compute_config()
2035 pipe_config->dsc_params.slice_count = in intel_dp_dsc_compute_config()
2043 intel_dp_dsc_get_output_bpp(pipe_config->port_clock, in intel_dp_dsc_compute_config()
2044 pipe_config->lane_count, in intel_dp_dsc_compute_config()
2055 pipe_config->dsc_params.compressed_bpp = min_t(u16, in intel_dp_dsc_compute_config()
2057 pipe_config->pipe_bpp); in intel_dp_dsc_compute_config()
2058 pipe_config->dsc_params.slice_count = dsc_dp_slice_count; in intel_dp_dsc_compute_config()
2066 if (pipe_config->dsc_params.slice_count > 1) { in intel_dp_dsc_compute_config()
2067 pipe_config->dsc_params.dsc_split = true; in intel_dp_dsc_compute_config()
2074 ret = intel_dp_compute_dsc_params(intel_dp, pipe_config); in intel_dp_dsc_compute_config()
2078 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
2079 pipe_config->dsc_params.compressed_bpp); in intel_dp_dsc_compute_config()
2083 pipe_config->dsc_params.compression_enable = true; in intel_dp_dsc_compute_config()
2086 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
2087 pipe_config->dsc_params.compressed_bpp, in intel_dp_dsc_compute_config()
2088 pipe_config->dsc_params.slice_count); in intel_dp_dsc_compute_config()
2103 struct intel_crtc_state *pipe_config, in intel_dp_compute_link_config() argument
2106 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_compute_link_config()
2124 limits.min_bpp = intel_dp_min_bpp(pipe_config); in intel_dp_compute_link_config()
2125 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); in intel_dp_compute_link_config()
2139 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); in intel_dp_compute_link_config()
2151 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); in intel_dp_compute_link_config()
2156 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, in intel_dp_compute_link_config()
2162 if (pipe_config->dsc_params.compression_enable) { in intel_dp_compute_link_config()
2164 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
2165 pipe_config->pipe_bpp, in intel_dp_compute_link_config()
2166 pipe_config->dsc_params.compressed_bpp); in intel_dp_compute_link_config()
2170 pipe_config->dsc_params.compressed_bpp), in intel_dp_compute_link_config()
2171 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
2172 pipe_config->lane_count)); in intel_dp_compute_link_config()
2175 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
2176 pipe_config->pipe_bpp); in intel_dp_compute_link_config()
2180 pipe_config->pipe_bpp), in intel_dp_compute_link_config()
2181 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
2182 pipe_config->lane_count)); in intel_dp_compute_link_config()
2242 struct intel_crtc_state *pipe_config, in intel_dp_compute_config() argument
2246 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_compute_config()
2250 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); in intel_dp_compute_config()
2259 pipe_config->has_pch_encoder = true; in intel_dp_compute_config()
2261 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dp_compute_config()
2263 lspcon_ycbcr420_config(&intel_connector->base, pipe_config); in intel_dp_compute_config()
2266 pipe_config); in intel_dp_compute_config()
2271 pipe_config->has_drrs = false; in intel_dp_compute_config()
2273 pipe_config->has_audio = false; in intel_dp_compute_config()
2275 pipe_config->has_audio = intel_dp->has_audio; in intel_dp_compute_config()
2277 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; in intel_dp_compute_config()
2284 ret = skl_update_scaler_crtc(pipe_config); in intel_dp_compute_config()
2290 intel_gmch_panel_fitting(intel_crtc, pipe_config, in intel_dp_compute_config()
2293 intel_pch_panel_fitting(intel_crtc, pipe_config, in intel_dp_compute_config()
2307 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); in intel_dp_compute_config()
2311 pipe_config->limited_color_range = in intel_dp_compute_config()
2312 intel_dp_limited_color_range(pipe_config, conn_state); in intel_dp_compute_config()
2314 if (pipe_config->dsc_params.compression_enable) in intel_dp_compute_config()
2315 output_bpp = pipe_config->dsc_params.compressed_bpp; in intel_dp_compute_config()
2317 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp); in intel_dp_compute_config()
2320 pipe_config->lane_count, in intel_dp_compute_config()
2322 pipe_config->port_clock, in intel_dp_compute_config()
2323 &pipe_config->dp_m_n, in intel_dp_compute_config()
2324 constant_n, pipe_config->fec_enable); in intel_dp_compute_config()
2328 pipe_config->has_drrs = true; in intel_dp_compute_config()
2330 pipe_config->lane_count, in intel_dp_compute_config()
2332 pipe_config->port_clock, in intel_dp_compute_config()
2333 &pipe_config->dp_m2_n2, in intel_dp_compute_config()
2334 constant_n, pipe_config->fec_enable); in intel_dp_compute_config()
2338 intel_dp_set_clock(encoder, pipe_config); in intel_dp_compute_config()
2340 intel_psr_compute_config(intel_dp, pipe_config); in intel_dp_compute_config()
2356 const struct intel_crtc_state *pipe_config) in intel_dp_prepare() argument
2361 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); in intel_dp_prepare()
2362 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_prepare()
2364 intel_dp_set_link_params(intel_dp, pipe_config->port_clock, in intel_dp_prepare()
2365 pipe_config->lane_count, in intel_dp_prepare()
2366 intel_crtc_has_type(pipe_config, in intel_dp_prepare()
2393 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); in intel_dp_prepare()
2420 if (IS_G4X(dev_priv) && pipe_config->limited_color_range) in intel_dp_prepare()
2947 const struct intel_crtc_state *pipe_config) in ironlake_edp_pll_on() argument
2949 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); in ironlake_edp_pll_on()
2957 pipe_config->port_clock); in ironlake_edp_pll_on()
2961 if (pipe_config->port_clock == 162000) in ironlake_edp_pll_on()
3143 struct intel_crtc_state *pipe_config) in intel_dp_get_config() argument
3149 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); in intel_dp_get_config()
3152 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); in intel_dp_get_config()
3154 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); in intel_dp_get_config()
3158 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; in intel_dp_get_config()
3184 pipe_config->base.adjusted_mode.flags |= flags; in intel_dp_get_config()
3187 pipe_config->limited_color_range = true; in intel_dp_get_config()
3189 pipe_config->lane_count = in intel_dp_get_config()
3192 intel_dp_get_m_n(crtc, pipe_config); in intel_dp_get_config()
3196 pipe_config->port_clock = 162000; in intel_dp_get_config()
3198 pipe_config->port_clock = 270000; in intel_dp_get_config()
3201 pipe_config->base.adjusted_mode.crtc_clock = in intel_dp_get_config()
3202 intel_dotclock_calculate(pipe_config->port_clock, in intel_dp_get_config()
3203 &pipe_config->dp_m_n); in intel_dp_get_config()
3206 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_dp_get_config()
3221 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); in intel_dp_get_config()
3222 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; in intel_dp_get_config()
3411 const struct intel_crtc_state *pipe_config, in intel_enable_dp() argument
3416 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); in intel_enable_dp()
3426 vlv_init_panel_power_sequencer(encoder, pipe_config); in intel_enable_dp()
3428 intel_dp_enable_port(intel_dp, pipe_config); in intel_enable_dp()
3439 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); in intel_enable_dp()
3449 if (pipe_config->has_audio) { in intel_enable_dp()
3452 intel_audio_codec_enable(encoder, pipe_config, conn_state); in intel_enable_dp()
3457 const struct intel_crtc_state *pipe_config, in g4x_enable_dp() argument
3460 intel_enable_dp(encoder, pipe_config, conn_state); in g4x_enable_dp()
3461 intel_edp_backlight_on(pipe_config, conn_state); in g4x_enable_dp()
3465 const struct intel_crtc_state *pipe_config, in vlv_enable_dp() argument
3468 intel_edp_backlight_on(pipe_config, conn_state); in vlv_enable_dp()
3472 const struct intel_crtc_state *pipe_config, in g4x_pre_enable_dp() argument
3478 intel_dp_prepare(encoder, pipe_config); in g4x_pre_enable_dp()
3482 ironlake_edp_pll_on(intel_dp, pipe_config); in g4x_pre_enable_dp()
3586 const struct intel_crtc_state *pipe_config, in vlv_pre_enable_dp() argument
3589 vlv_phy_pre_encoder_enable(encoder, pipe_config); in vlv_pre_enable_dp()
3591 intel_enable_dp(encoder, pipe_config, conn_state); in vlv_pre_enable_dp()
3595 const struct intel_crtc_state *pipe_config, in vlv_dp_pre_pll_enable() argument
3598 intel_dp_prepare(encoder, pipe_config); in vlv_dp_pre_pll_enable()
3600 vlv_phy_pre_pll_enable(encoder, pipe_config); in vlv_dp_pre_pll_enable()
3604 const struct intel_crtc_state *pipe_config, in chv_pre_enable_dp() argument
3607 chv_phy_pre_encoder_enable(encoder, pipe_config); in chv_pre_enable_dp()
3609 intel_enable_dp(encoder, pipe_config, conn_state); in chv_pre_enable_dp()
3616 const struct intel_crtc_state *pipe_config, in chv_dp_pre_pll_enable() argument
3619 intel_dp_prepare(encoder, pipe_config); in chv_dp_pre_pll_enable()
3621 chv_phy_pre_pll_enable(encoder, pipe_config); in chv_dp_pre_pll_enable()