Lines Matching refs:p2
1165 unsigned int *p2 /* out */) in skl_wrpll_get_multipliers() argument
1174 *p2 = half; in skl_wrpll_get_multipliers()
1178 *p2 = 2; in skl_wrpll_get_multipliers()
1182 *p2 = 2; in skl_wrpll_get_multipliers()
1186 *p2 = 2; in skl_wrpll_get_multipliers()
1191 *p2 = p / 3; in skl_wrpll_get_multipliers()
1195 *p2 = 1; in skl_wrpll_get_multipliers()
1199 *p2 = 5; in skl_wrpll_get_multipliers()
1203 *p2 = 3; in skl_wrpll_get_multipliers()
1207 *p2 = 5; in skl_wrpll_get_multipliers()
1224 u32 p0, u32 p1, u32 p2) in skl_wrpll_params_populate() argument
1256 switch (p2) { in skl_wrpll_params_populate()
1276 dco_freq = p0 * p1 * p2 * afe_clock; in skl_wrpll_params_populate()
1311 unsigned int p0, p1, p2; in skl_ddi_calculate_wrpll() local
1353 p0 = p1 = p2 = 0; in skl_ddi_calculate_wrpll()
1354 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); in skl_ddi_calculate_wrpll()
1356 p0, p1, p2); in skl_ddi_calculate_wrpll()
1728 u32 p2; member
1768 clk_div->p2 = best_clock.p2; in bxt_ddi_hdmi_pll_dividers()
1794 clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2; in bxt_ddi_dp_pll_dividers()
1840 dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2); in bxt_ddi_set_dpll_hw_state()