Lines Matching refs:dev_priv
187 struct drm_i915_private *dev_priv; member
257 void (*get_cdclk)(struct drm_i915_private *dev_priv,
259 void (*set_cdclk)(struct drm_i915_private *dev_priv,
262 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
296 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
297 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
514 struct drm_i915_private *dev_priv; member
1079 struct drm_i915_private *dev_priv; member
1219 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1226 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1232 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1835 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) argument
1836 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) argument
1837 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) argument
1839 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) argument
1840 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) argument
1843 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) argument
1851 #define IS_GEN_RANGE(dev_priv, s, e) \ argument
1852 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1854 #define IS_GEN(dev_priv, n) \ argument
1856 INTEL_INFO(dev_priv)->gen == (n))
1928 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) argument
1930 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) argument
1931 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) argument
1932 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) argument
1933 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) argument
1934 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) argument
1935 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) argument
1936 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) argument
1937 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) argument
1938 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) argument
1939 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) argument
1940 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) argument
1941 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) argument
1942 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) argument
1943 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) argument
1944 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) argument
1945 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) argument
1946 #define IS_IRONLAKE_M(dev_priv) \ argument
1947 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1948 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) argument
1949 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ argument
1950 INTEL_INFO(dev_priv)->gt == 1)
1951 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) argument
1952 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) argument
1953 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) argument
1954 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) argument
1955 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) argument
1956 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) argument
1957 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) argument
1958 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) argument
1959 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) argument
1960 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) argument
1961 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) argument
1962 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) argument
1963 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) argument
1964 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ argument
1965 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1966 #define IS_BDW_ULT(dev_priv) \ argument
1967 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1968 #define IS_BDW_ULX(dev_priv) \ argument
1969 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1970 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ argument
1971 INTEL_INFO(dev_priv)->gt == 3)
1972 #define IS_HSW_ULT(dev_priv) \ argument
1973 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1974 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ argument
1975 INTEL_INFO(dev_priv)->gt == 3)
1976 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ argument
1977 INTEL_INFO(dev_priv)->gt == 1)
1979 #define IS_HSW_ULX(dev_priv) \ argument
1980 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1981 #define IS_SKL_ULT(dev_priv) \ argument
1982 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1983 #define IS_SKL_ULX(dev_priv) \ argument
1984 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1985 #define IS_KBL_ULT(dev_priv) \ argument
1986 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1987 #define IS_KBL_ULX(dev_priv) \ argument
1988 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1989 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ argument
1990 INTEL_INFO(dev_priv)->gt == 2)
1991 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ argument
1992 INTEL_INFO(dev_priv)->gt == 3)
1993 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ argument
1994 INTEL_INFO(dev_priv)->gt == 4)
1995 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ argument
1996 INTEL_INFO(dev_priv)->gt == 2)
1997 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ argument
1998 INTEL_INFO(dev_priv)->gt == 3)
1999 #define IS_CFL_ULT(dev_priv) \ argument
2000 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
2001 #define IS_CFL_ULX(dev_priv) \ argument
2002 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
2003 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ argument
2004 INTEL_INFO(dev_priv)->gt == 2)
2005 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ argument
2006 INTEL_INFO(dev_priv)->gt == 3)
2007 #define IS_CNL_WITH_PORT_F(dev_priv) \ argument
2008 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
2009 #define IS_ICL_WITH_PORT_F(dev_priv) \ argument
2010 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
2029 #define IS_BXT_REVID(dev_priv, since, until) \ argument
2030 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2038 #define IS_KBL_REVID(dev_priv, since, until) \ argument
2039 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2044 #define IS_GLK_REVID(dev_priv, since, until) \ argument
2045 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2063 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) argument
2064 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) argument
2065 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) argument
2067 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) argument
2069 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ argument
2072 (INTEL_INFO(dev_priv)->engine_mask & \
2075 #define VDBOX_MASK(dev_priv) \ argument
2076 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
2077 #define VEBOX_MASK(dev_priv) \ argument
2078 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
2084 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) argument
2086 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) argument
2087 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) argument
2088 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) argument
2089 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) argument
2090 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ argument
2091 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2093 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) argument
2095 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ argument
2096 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2097 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ argument
2098 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2099 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ argument
2100 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2102 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) argument
2104 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) argument
2105 #define HAS_PPGTT(dev_priv) \ argument
2106 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2107 #define HAS_FULL_PPGTT(dev_priv) \ argument
2108 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2110 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ argument
2112 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2115 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) argument
2116 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ argument
2117 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2120 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) argument
2122 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ argument
2123 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
2126 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ argument
2127 (IS_CANNONLAKE(dev_priv) || IS_GEN(dev_priv, 9))
2129 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) argument
2130 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ argument
2131 IS_GEMINILAKE(dev_priv) || \
2132 IS_KABYLAKE(dev_priv))
2137 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ argument
2138 !(IS_I915G(dev_priv) || \
2139 IS_I915GM(dev_priv)))
2140 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) argument
2141 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) argument
2143 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) argument
2144 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) argument
2145 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) argument
2147 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) argument
2149 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) argument
2151 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) argument
2152 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) argument
2153 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) argument
2154 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0) argument
2156 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) argument
2157 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) argument
2158 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ argument
2160 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) argument
2162 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) argument
2164 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) argument
2165 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) argument
2167 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) argument
2169 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) argument
2172 #define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc) argument
2173 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc) argument
2175 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) argument
2177 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) argument
2180 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) argument
2182 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) argument
2185 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) argument
2186 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ argument
2187 2 : HAS_L3_DPF(dev_priv))
2192 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0) argument
2203 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) in intel_scanout_needs_vtd_wa() argument
2205 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); in intel_scanout_needs_vtd_wa()
2209 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) in intel_ggtt_update_needs_vtd_wa() argument
2211 return IS_BROXTON(dev_priv) && intel_vtd_active(); in intel_ggtt_update_needs_vtd_wa()
2226 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2228 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) in intel_gvt_active() argument
2230 return dev_priv->gvt; in intel_gvt_active()
2233 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) in intel_vgpu_active() argument
2235 return dev_priv->vgpu.active; in intel_vgpu_active()
2242 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2243 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2245 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2246 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2247 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2248 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2306 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2335 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
2336 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
2339 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
2340 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
2341 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
2343 void i915_gem_suspend(struct drm_i915_private *dev_priv);
2344 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
2345 void i915_gem_resume(struct drm_i915_private *dev_priv);
2392 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
2398 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); in i915_gem_object_needs_bit17_swizzle() local
2400 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && in i915_gem_object_needs_bit17_swizzle()
2404 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
2406 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
2412 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
2426 mkwrite_device_info(struct drm_i915_private *dev_priv) in mkwrite_device_info() argument
2428 return (struct intel_device_info *)INTEL_INFO(dev_priv); in mkwrite_device_info()
2437 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
2438 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
2440 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
2468 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2469 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))