2149 #define MG_MISC_SUS0(tc_port) \  argument
2176 #define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)	(0xf << (4 * (tc_port)))  argument
2177 #define   DFLEXDPMLE1_DPMLETC_ML0(tc_port)	(1 << (4 * (tc_port)))  argument
2178 #define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port)	(3 << (4 * (tc_port)))  argument
2179 #define   DFLEXDPMLE1_DPMLETC_ML3(tc_port)	(8 << (4 * (tc_port)))  argument
2180 #define   DFLEXDPMLE1_DPMLETC_ML3_2(tc_port)	(12 << (4 * (tc_port)))  argument
2181 #define   DFLEXDPMLE1_DPMLETC_ML3_0(tc_port)	(15 << (4 * (tc_port)))  argument
7431 #define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))  argument
7444 #define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))  argument
7454 #define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)		(8 << (tc_port) * 4)  argument
7455 #define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)		(2 << (tc_port) * 4)  argument
7456 #define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)  argument
7457 #define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)  argument
7847 #define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))  argument
7948 #define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)  argument
8053 #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)  argument
8054 #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)  argument
9745 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \  argument
9768 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \  argument
9777 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \  argument
9789 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \  argument
9809 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \  argument
9823 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \  argument
9838 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \  argument
9851 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \  argument
9864 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \  argument
9878 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \  argument
9898 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \  argument
9910 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \  argument
11546 #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))  argument
11547 #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))  argument
11548 #define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)  argument
11549 #define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))  argument
11550 #define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))  argument
11553 #define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)		(1 << (tc_port))  argument
11556 #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1 << (tc_port))  argument