Lines Matching refs:rps
6544 struct intel_rps *rps = &dev_priv->gt_pm.rps; in intel_rps_limits() local
6554 limits = (rps->max_freq_softlimit) << 23; in intel_rps_limits()
6555 if (val <= rps->min_freq_softlimit) in intel_rps_limits()
6556 limits |= (rps->min_freq_softlimit) << 14; in intel_rps_limits()
6558 limits = rps->max_freq_softlimit << 24; in intel_rps_limits()
6559 if (val <= rps->min_freq_softlimit) in intel_rps_limits()
6560 limits |= rps->min_freq_softlimit << 16; in intel_rps_limits()
6568 struct intel_rps *rps = &dev_priv->gt_pm.rps; in rps_set_power() local
6572 lockdep_assert_held(&rps->power.mutex); in rps_set_power()
6574 if (new_power == rps->power.mode) in rps_set_power()
6637 rps->power.mode = new_power; in rps_set_power()
6638 rps->power.up_threshold = threshold_up; in rps_set_power()
6639 rps->power.down_threshold = threshold_down; in rps_set_power()
6644 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_set_rps_thresholds() local
6647 new_power = rps->power.mode; in gen6_set_rps_thresholds()
6648 switch (rps->power.mode) { in gen6_set_rps_thresholds()
6650 if (val > rps->efficient_freq + 1 && in gen6_set_rps_thresholds()
6651 val > rps->cur_freq) in gen6_set_rps_thresholds()
6656 if (val <= rps->efficient_freq && in gen6_set_rps_thresholds()
6657 val < rps->cur_freq) in gen6_set_rps_thresholds()
6659 else if (val >= rps->rp0_freq && in gen6_set_rps_thresholds()
6660 val > rps->cur_freq) in gen6_set_rps_thresholds()
6665 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 && in gen6_set_rps_thresholds()
6666 val < rps->cur_freq) in gen6_set_rps_thresholds()
6671 if (val <= rps->min_freq_softlimit) in gen6_set_rps_thresholds()
6673 if (val >= rps->max_freq_softlimit) in gen6_set_rps_thresholds()
6676 mutex_lock(&rps->power.mutex); in gen6_set_rps_thresholds()
6677 if (rps->power.interactive) in gen6_set_rps_thresholds()
6680 mutex_unlock(&rps->power.mutex); in gen6_set_rps_thresholds()
6685 struct intel_rps *rps = &i915->gt_pm.rps; in intel_rps_mark_interactive() local
6690 mutex_lock(&rps->power.mutex); in intel_rps_mark_interactive()
6692 if (!rps->power.interactive++ && READ_ONCE(i915->gt.awake)) in intel_rps_mark_interactive()
6695 GEM_BUG_ON(!rps->power.interactive); in intel_rps_mark_interactive()
6696 rps->power.interactive--; in intel_rps_mark_interactive()
6698 mutex_unlock(&rps->power.mutex); in intel_rps_mark_interactive()
6703 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_rps_pm_mask() local
6707 if (val > rps->min_freq_softlimit) in gen6_rps_pm_mask()
6709 if (val < rps->max_freq_softlimit) in gen6_rps_pm_mask()
6722 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_set_rps() local
6727 if (val != rps->cur_freq) { in gen6_set_rps()
6749 rps->cur_freq = val; in gen6_set_rps()
6765 if (val != dev_priv->gt_pm.rps.cur_freq) { in valleyview_set_rps()
6775 dev_priv->gt_pm.rps.cur_freq = val; in valleyview_set_rps()
6790 struct intel_rps *rps = &dev_priv->gt_pm.rps; in vlv_set_rps_idle() local
6791 u32 val = rps->idle_freq; in vlv_set_rps_idle()
6794 if (rps->cur_freq <= val) in vlv_set_rps_idle()
6819 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_rps_busy() local
6821 mutex_lock(&rps->lock); in gen6_rps_busy()
6822 if (rps->enabled) { in gen6_rps_busy()
6828 gen6_rps_pm_mask(dev_priv, rps->cur_freq)); in gen6_rps_busy()
6835 freq = max(rps->cur_freq, in gen6_rps_busy()
6836 rps->efficient_freq); in gen6_rps_busy()
6840 rps->min_freq_softlimit, in gen6_rps_busy()
6841 rps->max_freq_softlimit))) in gen6_rps_busy()
6844 mutex_unlock(&rps->lock); in gen6_rps_busy()
6849 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_rps_idle() local
6858 mutex_lock(&rps->lock); in gen6_rps_idle()
6859 if (rps->enabled) { in gen6_rps_idle()
6863 gen6_set_rps(dev_priv, rps->idle_freq); in gen6_rps_idle()
6864 rps->last_adj = 0; in gen6_rps_idle()
6868 mutex_unlock(&rps->lock); in gen6_rps_idle()
6873 struct intel_rps *rps = &rq->i915->gt_pm.rps; in gen6_rps_boost() local
6880 if (!rps->enabled) in gen6_rps_boost()
6891 boost = !atomic_fetch_inc(&rps->num_waiters); in gen6_rps_boost()
6898 if (READ_ONCE(rps->cur_freq) < rps->boost_freq) in gen6_rps_boost()
6899 schedule_work(&rps->work); in gen6_rps_boost()
6901 atomic_inc(&rps->boosts); in gen6_rps_boost()
6906 struct intel_rps *rps = &dev_priv->gt_pm.rps; in intel_set_rps() local
6909 lockdep_assert_held(&rps->lock); in intel_set_rps()
6910 GEM_BUG_ON(val > rps->max_freq); in intel_set_rps()
6911 GEM_BUG_ON(val < rps->min_freq); in intel_set_rps()
6913 if (!rps->enabled) { in intel_set_rps()
6914 rps->cur_freq = val; in intel_set_rps()
7064 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_init_rps_frequencies() local
7071 rps->rp0_freq = (rp_state_cap >> 16) & 0xff; in gen6_init_rps_frequencies()
7072 rps->rp1_freq = (rp_state_cap >> 8) & 0xff; in gen6_init_rps_frequencies()
7073 rps->min_freq = (rp_state_cap >> 0) & 0xff; in gen6_init_rps_frequencies()
7076 rps->rp0_freq = (rp_state_cap >> 0) & 0xff; in gen6_init_rps_frequencies()
7077 rps->rp1_freq = (rp_state_cap >> 8) & 0xff; in gen6_init_rps_frequencies()
7078 rps->min_freq = (rp_state_cap >> 16) & 0xff; in gen6_init_rps_frequencies()
7081 rps->max_freq = rps->rp0_freq; in gen6_init_rps_frequencies()
7083 rps->efficient_freq = rps->rp1_freq; in gen6_init_rps_frequencies()
7091 rps->efficient_freq = in gen6_init_rps_frequencies()
7094 rps->min_freq, in gen6_init_rps_frequencies()
7095 rps->max_freq); in gen6_init_rps_frequencies()
7102 rps->rp0_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
7103 rps->rp1_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
7104 rps->min_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
7105 rps->max_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
7106 rps->efficient_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
7113 struct intel_rps *rps = &dev_priv->gt_pm.rps; in reset_rps() local
7114 u8 freq = rps->cur_freq; in reset_rps()
7117 rps->power.mode = -1; in reset_rps()
7118 rps->cur_freq = -1; in reset_rps()
7132 GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq)); in gen9_enable_rps()
7347 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen8_enable_rps() local
7353 HSW_FREQUENCY(rps->rp1_freq)); in gen8_enable_rps()
7355 HSW_FREQUENCY(rps->rp1_freq)); in gen8_enable_rps()
7361 rps->max_freq_softlimit << 24 | in gen8_enable_rps()
7362 rps->min_freq_softlimit << 16); in gen8_enable_rps()
7475 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_update_ring_freq() local
7483 lockdep_assert_held(&rps->lock); in gen6_update_ring_freq()
7485 if (rps->max_freq <= rps->min_freq) in gen6_update_ring_freq()
7507 min_gpu_freq = rps->min_freq; in gen6_update_ring_freq()
7508 max_gpu_freq = rps->max_freq; in gen6_update_ring_freq()
7766 dev_priv->gt_pm.rps.gpll_ref_freq = in vlv_init_gpll_ref_freq()
7772 dev_priv->gt_pm.rps.gpll_ref_freq); in vlv_init_gpll_ref_freq()
7777 struct intel_rps *rps = &dev_priv->gt_pm.rps; in valleyview_init_gt_powersave() local
7804 rps->max_freq = valleyview_rps_max_freq(dev_priv); in valleyview_init_gt_powersave()
7805 rps->rp0_freq = rps->max_freq; in valleyview_init_gt_powersave()
7807 intel_gpu_freq(dev_priv, rps->max_freq), in valleyview_init_gt_powersave()
7808 rps->max_freq); in valleyview_init_gt_powersave()
7810 rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv); in valleyview_init_gt_powersave()
7812 intel_gpu_freq(dev_priv, rps->efficient_freq), in valleyview_init_gt_powersave()
7813 rps->efficient_freq); in valleyview_init_gt_powersave()
7815 rps->rp1_freq = valleyview_rps_guar_freq(dev_priv); in valleyview_init_gt_powersave()
7817 intel_gpu_freq(dev_priv, rps->rp1_freq), in valleyview_init_gt_powersave()
7818 rps->rp1_freq); in valleyview_init_gt_powersave()
7820 rps->min_freq = valleyview_rps_min_freq(dev_priv); in valleyview_init_gt_powersave()
7822 intel_gpu_freq(dev_priv, rps->min_freq), in valleyview_init_gt_powersave()
7823 rps->min_freq); in valleyview_init_gt_powersave()
7833 struct intel_rps *rps = &dev_priv->gt_pm.rps; in cherryview_init_gt_powersave() local
7857 rps->max_freq = cherryview_rps_max_freq(dev_priv); in cherryview_init_gt_powersave()
7858 rps->rp0_freq = rps->max_freq; in cherryview_init_gt_powersave()
7860 intel_gpu_freq(dev_priv, rps->max_freq), in cherryview_init_gt_powersave()
7861 rps->max_freq); in cherryview_init_gt_powersave()
7863 rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv); in cherryview_init_gt_powersave()
7865 intel_gpu_freq(dev_priv, rps->efficient_freq), in cherryview_init_gt_powersave()
7866 rps->efficient_freq); in cherryview_init_gt_powersave()
7868 rps->rp1_freq = cherryview_rps_guar_freq(dev_priv); in cherryview_init_gt_powersave()
7870 intel_gpu_freq(dev_priv, rps->rp1_freq), in cherryview_init_gt_powersave()
7871 rps->rp1_freq); in cherryview_init_gt_powersave()
7873 rps->min_freq = cherryview_rps_min_freq(dev_priv); in cherryview_init_gt_powersave()
7875 intel_gpu_freq(dev_priv, rps->min_freq), in cherryview_init_gt_powersave()
7876 rps->min_freq); in cherryview_init_gt_powersave()
7883 WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq | in cherryview_init_gt_powersave()
7884 rps->min_freq) & 1, in cherryview_init_gt_powersave()
8267 pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq)); in __i915_gfx_val()
8651 struct intel_rps *rps = &dev_priv->gt_pm.rps; in intel_init_gt_powersave() local
8673 rps->max_freq_softlimit = rps->max_freq; in intel_init_gt_powersave()
8674 rps->min_freq_softlimit = rps->min_freq; in intel_init_gt_powersave()
8685 (rps->max_freq & 0xff) * 50, in intel_init_gt_powersave()
8687 rps->max_freq = params & 0xff; in intel_init_gt_powersave()
8692 rps->boost_freq = rps->max_freq; in intel_init_gt_powersave()
8693 rps->idle_freq = rps->min_freq; in intel_init_gt_powersave()
8694 rps->cur_freq = rps->idle_freq; in intel_init_gt_powersave()
8710 dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */ in intel_sanitize_gt_powersave()
8722 lockdep_assert_held(&i915->gt_pm.rps.lock); in intel_disable_llc_pstate()
8734 lockdep_assert_held(&dev_priv->gt_pm.rps.lock); in __intel_disable_rc6()
8753 struct intel_rps *rps = &dev_priv->gt_pm.rps; in intel_disable_rc6() local
8755 mutex_lock(&rps->lock); in intel_disable_rc6()
8757 mutex_unlock(&rps->lock); in intel_disable_rc6()
8762 lockdep_assert_held(&dev_priv->gt_pm.rps.lock); in intel_disable_rps()
8764 if (!dev_priv->gt_pm.rps.enabled) in intel_disable_rps()
8778 dev_priv->gt_pm.rps.enabled = false; in intel_disable_rps()
8783 mutex_lock(&dev_priv->gt_pm.rps.lock); in intel_disable_gt_powersave()
8790 mutex_unlock(&dev_priv->gt_pm.rps.lock); in intel_disable_gt_powersave()
8795 lockdep_assert_held(&i915->gt_pm.rps.lock); in intel_enable_llc_pstate()
8807 lockdep_assert_held(&dev_priv->gt_pm.rps.lock); in intel_enable_rc6()
8833 struct intel_rps *rps = &dev_priv->gt_pm.rps; in intel_enable_rps() local
8835 lockdep_assert_held(&rps->lock); in intel_enable_rps()
8837 if (rps->enabled) in intel_enable_rps()
8855 WARN_ON(rps->max_freq < rps->min_freq); in intel_enable_rps()
8856 WARN_ON(rps->idle_freq > rps->max_freq); in intel_enable_rps()
8858 WARN_ON(rps->efficient_freq < rps->min_freq); in intel_enable_rps()
8859 WARN_ON(rps->efficient_freq > rps->max_freq); in intel_enable_rps()
8861 rps->enabled = true; in intel_enable_rps()
8870 mutex_lock(&dev_priv->gt_pm.rps.lock); in intel_enable_gt_powersave()
8879 mutex_unlock(&dev_priv->gt_pm.rps.lock); in intel_enable_gt_powersave()
9858 struct intel_rps *rps = &dev_priv->gt_pm.rps; in byt_gpu_freq() local
9864 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000); in byt_gpu_freq()
9869 struct intel_rps *rps = &dev_priv->gt_pm.rps; in byt_freq_opcode() local
9871 return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7; in byt_freq_opcode()
9876 struct intel_rps *rps = &dev_priv->gt_pm.rps; in chv_gpu_freq() local
9882 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000); in chv_gpu_freq()
9887 struct intel_rps *rps = &dev_priv->gt_pm.rps; in chv_freq_opcode() local
9890 return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2; in chv_freq_opcode()
9921 mutex_init(&dev_priv->gt_pm.rps.lock); in intel_pm_setup()
9922 mutex_init(&dev_priv->gt_pm.rps.power.mutex); in intel_pm_setup()
9924 atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0); in intel_pm_setup()