10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static bool a2xx_me_init(struct msm_gpu *gpu)  in a2xx_me_init()  argument
15 	struct msm_ringbuffer *ring = gpu->rb[0];  in a2xx_me_init()
56 	gpu->funcs->flush(gpu, ring);  in a2xx_me_init()
57 	return a2xx_idle(gpu);  in a2xx_me_init()
60 static int a2xx_hw_init(struct msm_gpu *gpu)  in a2xx_hw_init()  argument
62 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a2xx_hw_init()
67 	msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);  in a2xx_hw_init()
69 	DBG("%s", gpu->name);  in a2xx_hw_init()
72 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, AXXX_CP_ME_CNTL_HALT);  in a2xx_hw_init()
74 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0xfffffffe);  in a2xx_hw_init()
75 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0xffffffff);  in a2xx_hw_init()
78 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0xffffffff);  in a2xx_hw_init()
80 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0x00000000);  in a2xx_hw_init()
83 		gpu_write(gpu, REG_A2XX_SQ_FLOW_CONTROL, 0x18000000);  in a2xx_hw_init()
86 	gpu_write(gpu, REG_A2XX_RBBM_CNTL, 0x00004442);  in a2xx_hw_init()
89 	gpu_write(gpu, REG_A2XX_MH_MMU_MPU_BASE, 0x00000000);  in a2xx_hw_init()
90 	gpu_write(gpu, REG_A2XX_MH_MMU_MPU_END, 0xfffff000);  in a2xx_hw_init()
92 	gpu_write(gpu, REG_A2XX_MH_MMU_CONFIG, A2XX_MH_MMU_CONFIG_MMU_ENABLE |  in a2xx_hw_init()
106 	gpu_write(gpu, REG_A2XX_MH_MMU_VA_RANGE, SZ_16M |  in a2xx_hw_init()
109 	gpu_write(gpu, REG_A2XX_MH_MMU_PT_BASE, pt_base);  in a2xx_hw_init()
110 	gpu_write(gpu, REG_A2XX_MH_MMU_TRAN_ERROR, tran_error);  in a2xx_hw_init()
112 	gpu_write(gpu, REG_A2XX_MH_MMU_INVALIDATE,  in a2xx_hw_init()
116 	gpu_write(gpu, REG_A2XX_MH_ARBITER_CONFIG,  in a2xx_hw_init()
131 		gpu_write(gpu, REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1, 0x00032f07);  in a2xx_hw_init()
133 	gpu_write(gpu, REG_A2XX_SQ_VS_PROGRAM, 0x00000000);  in a2xx_hw_init()
134 	gpu_write(gpu, REG_A2XX_SQ_PS_PROGRAM, 0x00000000);  in a2xx_hw_init()
136 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0); /* 0x200 for msm8960? */  in a2xx_hw_init()
137 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0); /* 0x80/0x1a0 for a22x? */  in a2xx_hw_init()
140 	gpu_write(gpu, REG_A2XX_RBBM_DEBUG, 0x00080000);  in a2xx_hw_init()
142 	gpu_write(gpu, REG_A2XX_RBBM_INT_CNTL,  in a2xx_hw_init()
144 	gpu_write(gpu, REG_AXXX_CP_INT_CNTL,  in a2xx_hw_init()
152 	gpu_write(gpu, REG_A2XX_SQ_INT_CNTL, 0);  in a2xx_hw_init()
153 	gpu_write(gpu, REG_A2XX_MH_INTERRUPT_MASK,  in a2xx_hw_init()
161 	gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i);  in a2xx_hw_init()
163 	ret = adreno_hw_init(gpu);  in a2xx_hw_init()
178 	gpu_write(gpu, REG_AXXX_CP_DEBUG,  in a2xx_hw_init()
180 	gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);  in a2xx_hw_init()
182 		gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);  in a2xx_hw_init()
189 	gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_ADDR, 0);  in a2xx_hw_init()
191 		gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_DATA, ptr[i]);  in a2xx_hw_init()
193 	gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x000C0804);  in a2xx_hw_init()
196 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);  in a2xx_hw_init()
198 	return a2xx_me_init(gpu) ? 0 : -EINVAL;  in a2xx_hw_init()
201 static void a2xx_recover(struct msm_gpu *gpu)  in a2xx_recover()  argument
205 	adreno_dump_info(gpu);  in a2xx_recover()
209 			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));  in a2xx_recover()
214 		a2xx_dump(gpu);  in a2xx_recover()
216 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 1);  in a2xx_recover()
217 	gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET);  in a2xx_recover()
218 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0);  in a2xx_recover()
219 	adreno_recover(gpu);  in a2xx_recover()
222 static void a2xx_destroy(struct msm_gpu *gpu)  in a2xx_destroy()  argument
224 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a2xx_destroy()
227 	DBG("%s", gpu->name);  in a2xx_destroy()
234 static bool a2xx_idle(struct msm_gpu *gpu)  in a2xx_idle()  argument
237 	if (!adreno_idle(gpu, gpu->rb[0]))  in a2xx_idle()
241 	if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) &  in a2xx_idle()
243 		DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);  in a2xx_idle()
252 static irqreturn_t a2xx_irq(struct msm_gpu *gpu)  in a2xx_irq()  argument
256 	mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL);  in a2xx_irq()
259 		status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS);  in a2xx_irq()
261 		dev_warn(gpu->dev->dev, "MH_INT: %08X\n", status);  in a2xx_irq()
262 		dev_warn(gpu->dev->dev, "MMU_PAGE_FAULT: %08X\n",  in a2xx_irq()
263 			gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT));  in a2xx_irq()
265 		gpu_write(gpu, REG_A2XX_MH_INTERRUPT_CLEAR, status);  in a2xx_irq()
269 		status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS);  in a2xx_irq()
273 			dev_warn(gpu->dev->dev, "CP_INT: %08X\n", status);  in a2xx_irq()
275 		gpu_write(gpu, REG_AXXX_CP_INT_ACK, status);  in a2xx_irq()
279 		status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS);  in a2xx_irq()
281 		dev_warn(gpu->dev->dev, "RBBM_INT: %08X\n", status);  in a2xx_irq()
283 		gpu_write(gpu, REG_A2XX_RBBM_INT_ACK, status);  in a2xx_irq()
286 	msm_gpu_retire(gpu);  in a2xx_irq()
383 static void a2xx_dump(struct msm_gpu *gpu)  in a2xx_dump()  argument
386 			gpu_read(gpu, REG_A2XX_RBBM_STATUS));  in a2xx_dump()
387 	adreno_dump(gpu);  in a2xx_dump()
390 static struct msm_gpu_state *a2xx_gpu_state_get(struct msm_gpu *gpu)  in a2xx_gpu_state_get()  argument
397 	adreno_gpu_state_get(gpu, state);  in a2xx_gpu_state_get()
399 	state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS);  in a2xx_gpu_state_get()
443 	struct msm_gpu *gpu;  in a2xx_gpu_init()  local
461 	gpu = &adreno_gpu->base;  in a2xx_gpu_init()
463 	gpu->perfcntrs = perfcntrs;  in a2xx_gpu_init()
464 	gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);  in a2xx_gpu_init()
479 	if (!gpu->aspace) {  in a2xx_gpu_init()
485 	return gpu;  in a2xx_gpu_init()