Lines Matching refs:gpu
28 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_target() local
36 if (gpu->funcs->gpu_set_freq) in msm_devfreq_target()
37 gpu->funcs->gpu_set_freq(gpu, (u64)*freq); in msm_devfreq_target()
39 clk_set_rate(gpu->core_clk, *freq); in msm_devfreq_target()
49 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_get_dev_status() local
52 if (gpu->funcs->gpu_get_freq) in msm_devfreq_get_dev_status()
53 status->current_frequency = gpu->funcs->gpu_get_freq(gpu); in msm_devfreq_get_dev_status()
55 status->current_frequency = clk_get_rate(gpu->core_clk); in msm_devfreq_get_dev_status()
57 status->busy_time = gpu->funcs->gpu_busy(gpu); in msm_devfreq_get_dev_status()
60 status->total_time = ktime_us_delta(time, gpu->devfreq.time); in msm_devfreq_get_dev_status()
61 gpu->devfreq.time = time; in msm_devfreq_get_dev_status()
68 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_get_cur_freq() local
70 if (gpu->funcs->gpu_get_freq) in msm_devfreq_get_cur_freq()
71 *freq = gpu->funcs->gpu_get_freq(gpu); in msm_devfreq_get_cur_freq()
73 *freq = clk_get_rate(gpu->core_clk); in msm_devfreq_get_cur_freq()
85 static void msm_devfreq_init(struct msm_gpu *gpu) in msm_devfreq_init() argument
88 if (!gpu->funcs->gpu_busy) in msm_devfreq_init()
91 msm_devfreq_profile.initial_freq = gpu->fast_rate; in msm_devfreq_init()
98 gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev, in msm_devfreq_init()
102 if (IS_ERR(gpu->devfreq.devfreq)) { in msm_devfreq_init()
103 DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n"); in msm_devfreq_init()
104 gpu->devfreq.devfreq = NULL; in msm_devfreq_init()
107 devfreq_suspend_device(gpu->devfreq.devfreq); in msm_devfreq_init()
110 static int enable_pwrrail(struct msm_gpu *gpu) in enable_pwrrail() argument
112 struct drm_device *dev = gpu->dev; in enable_pwrrail()
115 if (gpu->gpu_reg) { in enable_pwrrail()
116 ret = regulator_enable(gpu->gpu_reg); in enable_pwrrail()
123 if (gpu->gpu_cx) { in enable_pwrrail()
124 ret = regulator_enable(gpu->gpu_cx); in enable_pwrrail()
134 static int disable_pwrrail(struct msm_gpu *gpu) in disable_pwrrail() argument
136 if (gpu->gpu_cx) in disable_pwrrail()
137 regulator_disable(gpu->gpu_cx); in disable_pwrrail()
138 if (gpu->gpu_reg) in disable_pwrrail()
139 regulator_disable(gpu->gpu_reg); in disable_pwrrail()
143 static int enable_clk(struct msm_gpu *gpu) in enable_clk() argument
145 if (gpu->core_clk && gpu->fast_rate) in enable_clk()
146 clk_set_rate(gpu->core_clk, gpu->fast_rate); in enable_clk()
149 if (gpu->rbbmtimer_clk) in enable_clk()
150 clk_set_rate(gpu->rbbmtimer_clk, 19200000); in enable_clk()
152 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); in enable_clk()
155 static int disable_clk(struct msm_gpu *gpu) in disable_clk() argument
157 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); in disable_clk()
164 if (gpu->core_clk) in disable_clk()
165 clk_set_rate(gpu->core_clk, 27000000); in disable_clk()
167 if (gpu->rbbmtimer_clk) in disable_clk()
168 clk_set_rate(gpu->rbbmtimer_clk, 0); in disable_clk()
173 static int enable_axi(struct msm_gpu *gpu) in enable_axi() argument
175 if (gpu->ebi1_clk) in enable_axi()
176 clk_prepare_enable(gpu->ebi1_clk); in enable_axi()
180 static int disable_axi(struct msm_gpu *gpu) in disable_axi() argument
182 if (gpu->ebi1_clk) in disable_axi()
183 clk_disable_unprepare(gpu->ebi1_clk); in disable_axi()
187 void msm_gpu_resume_devfreq(struct msm_gpu *gpu) in msm_gpu_resume_devfreq() argument
189 gpu->devfreq.busy_cycles = 0; in msm_gpu_resume_devfreq()
190 gpu->devfreq.time = ktime_get(); in msm_gpu_resume_devfreq()
192 devfreq_resume_device(gpu->devfreq.devfreq); in msm_gpu_resume_devfreq()
195 int msm_gpu_pm_resume(struct msm_gpu *gpu) in msm_gpu_pm_resume() argument
199 DBG("%s", gpu->name); in msm_gpu_pm_resume()
201 ret = enable_pwrrail(gpu); in msm_gpu_pm_resume()
205 ret = enable_clk(gpu); in msm_gpu_pm_resume()
209 ret = enable_axi(gpu); in msm_gpu_pm_resume()
213 msm_gpu_resume_devfreq(gpu); in msm_gpu_pm_resume()
215 gpu->needs_hw_init = true; in msm_gpu_pm_resume()
220 int msm_gpu_pm_suspend(struct msm_gpu *gpu) in msm_gpu_pm_suspend() argument
224 DBG("%s", gpu->name); in msm_gpu_pm_suspend()
226 devfreq_suspend_device(gpu->devfreq.devfreq); in msm_gpu_pm_suspend()
228 ret = disable_axi(gpu); in msm_gpu_pm_suspend()
232 ret = disable_clk(gpu); in msm_gpu_pm_suspend()
236 ret = disable_pwrrail(gpu); in msm_gpu_pm_suspend()
243 int msm_gpu_hw_init(struct msm_gpu *gpu) in msm_gpu_hw_init() argument
247 WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex)); in msm_gpu_hw_init()
249 if (!gpu->needs_hw_init) in msm_gpu_hw_init()
252 disable_irq(gpu->irq); in msm_gpu_hw_init()
253 ret = gpu->funcs->hw_init(gpu); in msm_gpu_hw_init()
255 gpu->needs_hw_init = false; in msm_gpu_hw_init()
256 enable_irq(gpu->irq); in msm_gpu_hw_init()
265 struct msm_gpu *gpu = data; in msm_gpu_devcoredump_read() local
270 state = msm_gpu_crashstate_get(gpu); in msm_gpu_devcoredump_read()
291 gpu->funcs->show(gpu, state, &p); in msm_gpu_devcoredump_read()
293 msm_gpu_crashstate_put(gpu); in msm_gpu_devcoredump_read()
300 struct msm_gpu *gpu = data; in msm_gpu_devcoredump_free() local
302 msm_gpu_crashstate_put(gpu); in msm_gpu_devcoredump_free()
336 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, in msm_gpu_crashstate_capture() argument
342 if (!gpu->funcs->gpu_state_get) in msm_gpu_crashstate_capture()
346 if (gpu->crashstate) in msm_gpu_crashstate_capture()
349 state = gpu->funcs->gpu_state_get(gpu); in msm_gpu_crashstate_capture()
372 gpu->crashstate = state; in msm_gpu_crashstate_capture()
375 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, in msm_gpu_crashstate_capture()
379 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, in msm_gpu_crashstate_capture() argument
389 static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in update_fences() argument
408 WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex)); in find_submit()
417 static void retire_submits(struct msm_gpu *gpu);
421 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); in recover_worker() local
422 struct drm_device *dev = gpu->dev; in recover_worker()
425 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); in recover_worker()
431 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name); in recover_worker()
438 gpu->global_faults++; in recover_worker()
450 gpu->name, comm, cmd); in recover_worker()
459 pm_runtime_get_sync(&gpu->pdev->dev); in recover_worker()
460 msm_gpu_crashstate_capture(gpu, submit, comm, cmd); in recover_worker()
461 pm_runtime_put_sync(&gpu->pdev->dev); in recover_worker()
471 for (i = 0; i < gpu->nr_rings; i++) { in recover_worker()
472 struct msm_ringbuffer *ring = gpu->rb[i]; in recover_worker()
483 update_fences(gpu, ring, fence); in recover_worker()
486 if (msm_gpu_active(gpu)) { in recover_worker()
488 retire_submits(gpu); in recover_worker()
490 pm_runtime_get_sync(&gpu->pdev->dev); in recover_worker()
491 gpu->funcs->recover(gpu); in recover_worker()
492 pm_runtime_put_sync(&gpu->pdev->dev); in recover_worker()
498 for (i = 0; i < gpu->nr_rings; i++) { in recover_worker()
499 struct msm_ringbuffer *ring = gpu->rb[i]; in recover_worker()
502 gpu->funcs->submit(gpu, submit, NULL); in recover_worker()
508 msm_gpu_retire(gpu); in recover_worker()
511 static void hangcheck_timer_reset(struct msm_gpu *gpu) in hangcheck_timer_reset() argument
513 DBG("%s", gpu->name); in hangcheck_timer_reset()
514 mod_timer(&gpu->hangcheck_timer, in hangcheck_timer_reset()
520 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer); in hangcheck_handler() local
521 struct drm_device *dev = gpu->dev; in hangcheck_handler()
523 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in hangcheck_handler()
533 gpu->name, ring->id); in hangcheck_handler()
535 gpu->name, fence); in hangcheck_handler()
537 gpu->name, ring->seqno); in hangcheck_handler()
539 queue_work(priv->wq, &gpu->recover_work); in hangcheck_handler()
544 hangcheck_timer_reset(gpu); in hangcheck_handler()
547 queue_work(priv->wq, &gpu->retire_work); in hangcheck_handler()
555 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) in update_hw_cntrs() argument
557 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; in update_hw_cntrs()
558 int i, n = min(ncntrs, gpu->num_perfcntrs); in update_hw_cntrs()
561 for (i = 0; i < gpu->num_perfcntrs; i++) in update_hw_cntrs()
562 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); in update_hw_cntrs()
566 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; in update_hw_cntrs()
569 for (i = 0; i < gpu->num_perfcntrs; i++) in update_hw_cntrs()
570 gpu->last_cntrs[i] = current_cntrs[i]; in update_hw_cntrs()
575 static void update_sw_cntrs(struct msm_gpu *gpu) in update_sw_cntrs() argument
581 spin_lock_irqsave(&gpu->perf_lock, flags); in update_sw_cntrs()
582 if (!gpu->perfcntr_active) in update_sw_cntrs()
586 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); in update_sw_cntrs()
588 gpu->totaltime += elapsed; in update_sw_cntrs()
589 if (gpu->last_sample.active) in update_sw_cntrs()
590 gpu->activetime += elapsed; in update_sw_cntrs()
592 gpu->last_sample.active = msm_gpu_active(gpu); in update_sw_cntrs()
593 gpu->last_sample.time = time; in update_sw_cntrs()
596 spin_unlock_irqrestore(&gpu->perf_lock, flags); in update_sw_cntrs()
599 void msm_gpu_perfcntr_start(struct msm_gpu *gpu) in msm_gpu_perfcntr_start() argument
603 pm_runtime_get_sync(&gpu->pdev->dev); in msm_gpu_perfcntr_start()
605 spin_lock_irqsave(&gpu->perf_lock, flags); in msm_gpu_perfcntr_start()
607 gpu->last_sample.active = msm_gpu_active(gpu); in msm_gpu_perfcntr_start()
608 gpu->last_sample.time = ktime_get(); in msm_gpu_perfcntr_start()
609 gpu->activetime = gpu->totaltime = 0; in msm_gpu_perfcntr_start()
610 gpu->perfcntr_active = true; in msm_gpu_perfcntr_start()
611 update_hw_cntrs(gpu, 0, NULL); in msm_gpu_perfcntr_start()
612 spin_unlock_irqrestore(&gpu->perf_lock, flags); in msm_gpu_perfcntr_start()
615 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) in msm_gpu_perfcntr_stop() argument
617 gpu->perfcntr_active = false; in msm_gpu_perfcntr_stop()
618 pm_runtime_put_sync(&gpu->pdev->dev); in msm_gpu_perfcntr_stop()
622 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, in msm_gpu_perfcntr_sample() argument
628 spin_lock_irqsave(&gpu->perf_lock, flags); in msm_gpu_perfcntr_sample()
630 if (!gpu->perfcntr_active) { in msm_gpu_perfcntr_sample()
635 *activetime = gpu->activetime; in msm_gpu_perfcntr_sample()
636 *totaltime = gpu->totaltime; in msm_gpu_perfcntr_sample()
638 gpu->activetime = gpu->totaltime = 0; in msm_gpu_perfcntr_sample()
640 ret = update_hw_cntrs(gpu, ncntrs, cntrs); in msm_gpu_perfcntr_sample()
643 spin_unlock_irqrestore(&gpu->perf_lock, flags); in msm_gpu_perfcntr_sample()
652 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in retire_submit() argument
682 pm_runtime_mark_last_busy(&gpu->pdev->dev); in retire_submit()
683 pm_runtime_put_autosuspend(&gpu->pdev->dev); in retire_submit()
687 static void retire_submits(struct msm_gpu *gpu) in retire_submits() argument
689 struct drm_device *dev = gpu->dev; in retire_submits()
696 for (i = 0; i < gpu->nr_rings; i++) { in retire_submits()
697 struct msm_ringbuffer *ring = gpu->rb[i]; in retire_submits()
701 retire_submit(gpu, ring, submit); in retire_submits()
708 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); in retire_worker() local
709 struct drm_device *dev = gpu->dev; in retire_worker()
712 for (i = 0; i < gpu->nr_rings; i++) in retire_worker()
713 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence); in retire_worker()
716 retire_submits(gpu); in retire_worker()
721 void msm_gpu_retire(struct msm_gpu *gpu) in msm_gpu_retire() argument
723 struct msm_drm_private *priv = gpu->dev->dev_private; in msm_gpu_retire()
724 queue_work(priv->wq, &gpu->retire_work); in msm_gpu_retire()
725 update_sw_cntrs(gpu); in msm_gpu_retire()
729 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, in msm_gpu_submit() argument
732 struct drm_device *dev = gpu->dev; in msm_gpu_submit()
739 pm_runtime_get_sync(&gpu->pdev->dev); in msm_gpu_submit()
741 msm_gpu_hw_init(gpu); in msm_gpu_submit()
749 update_sw_cntrs(gpu); in msm_gpu_submit()
758 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu)); in msm_gpu_submit()
765 msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence); in msm_gpu_submit()
767 msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence); in msm_gpu_submit()
770 gpu->funcs->submit(gpu, submit, ctx); in msm_gpu_submit()
773 hangcheck_timer_reset(gpu); in msm_gpu_submit()
782 struct msm_gpu *gpu = data; in irq_handler() local
783 return gpu->funcs->irq(gpu); in irq_handler()
786 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) in get_clocks() argument
788 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks); in get_clocks()
791 gpu->nr_clocks = 0; in get_clocks()
795 gpu->nr_clocks = ret; in get_clocks()
797 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, in get_clocks()
798 gpu->nr_clocks, "core"); in get_clocks()
800 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, in get_clocks()
801 gpu->nr_clocks, "rbbmtimer"); in get_clocks()
807 msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev, in msm_gpu_create_address_space() argument
818 if (!adreno_is_a2xx(to_adreno_gpu(gpu))) { in msm_gpu_create_address_space()
826 DRM_DEV_INFO(gpu->dev->dev, "%s: using IOMMU\n", gpu->name); in msm_gpu_create_address_space()
832 aspace = msm_gem_address_space_create_a2xx(&pdev->dev, gpu, "gpu", in msm_gpu_create_address_space()
837 DRM_DEV_ERROR(gpu->dev->dev, "failed to init mmu: %ld\n", in msm_gpu_create_address_space()
852 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, in msm_gpu_init() argument
859 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) in msm_gpu_init()
860 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); in msm_gpu_init()
862 gpu->dev = drm; in msm_gpu_init()
863 gpu->funcs = funcs; in msm_gpu_init()
864 gpu->name = name; in msm_gpu_init()
866 INIT_LIST_HEAD(&gpu->active_list); in msm_gpu_init()
867 INIT_WORK(&gpu->retire_work, retire_worker); in msm_gpu_init()
868 INIT_WORK(&gpu->recover_work, recover_worker); in msm_gpu_init()
871 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); in msm_gpu_init()
873 spin_lock_init(&gpu->perf_lock); in msm_gpu_init()
877 gpu->mmio = msm_ioremap(pdev, config->ioname, name); in msm_gpu_init()
878 if (IS_ERR(gpu->mmio)) { in msm_gpu_init()
879 ret = PTR_ERR(gpu->mmio); in msm_gpu_init()
884 gpu->irq = platform_get_irq(pdev, 0); in msm_gpu_init()
885 if (gpu->irq < 0) { in msm_gpu_init()
886 ret = gpu->irq; in msm_gpu_init()
891 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, in msm_gpu_init()
892 IRQF_TRIGGER_HIGH, gpu->name, gpu); in msm_gpu_init()
894 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); in msm_gpu_init()
898 ret = get_clocks(pdev, gpu); in msm_gpu_init()
902 gpu->ebi1_clk = msm_clk_get(pdev, "bus"); in msm_gpu_init()
903 DBG("ebi1_clk: %p", gpu->ebi1_clk); in msm_gpu_init()
904 if (IS_ERR(gpu->ebi1_clk)) in msm_gpu_init()
905 gpu->ebi1_clk = NULL; in msm_gpu_init()
908 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); in msm_gpu_init()
909 DBG("gpu_reg: %p", gpu->gpu_reg); in msm_gpu_init()
910 if (IS_ERR(gpu->gpu_reg)) in msm_gpu_init()
911 gpu->gpu_reg = NULL; in msm_gpu_init()
913 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); in msm_gpu_init()
914 DBG("gpu_cx: %p", gpu->gpu_cx); in msm_gpu_init()
915 if (IS_ERR(gpu->gpu_cx)) in msm_gpu_init()
916 gpu->gpu_cx = NULL; in msm_gpu_init()
918 gpu->pdev = pdev; in msm_gpu_init()
919 platform_set_drvdata(pdev, gpu); in msm_gpu_init()
921 msm_devfreq_init(gpu); in msm_gpu_init()
923 gpu->aspace = msm_gpu_create_address_space(gpu, pdev, in msm_gpu_init()
926 if (gpu->aspace == NULL) in msm_gpu_init()
928 else if (IS_ERR(gpu->aspace)) { in msm_gpu_init()
929 ret = PTR_ERR(gpu->aspace); in msm_gpu_init()
935 MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo, in msm_gpu_init()
944 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs"); in msm_gpu_init()
946 if (nr_rings > ARRAY_SIZE(gpu->rb)) { in msm_gpu_init()
948 ARRAY_SIZE(gpu->rb)); in msm_gpu_init()
949 nr_rings = ARRAY_SIZE(gpu->rb); in msm_gpu_init()
954 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); in msm_gpu_init()
956 if (IS_ERR(gpu->rb[i])) { in msm_gpu_init()
957 ret = PTR_ERR(gpu->rb[i]); in msm_gpu_init()
967 gpu->nr_rings = nr_rings; in msm_gpu_init()
972 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { in msm_gpu_init()
973 msm_ringbuffer_destroy(gpu->rb[i]); in msm_gpu_init()
974 gpu->rb[i] = NULL; in msm_gpu_init()
977 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false); in msm_gpu_init()
983 void msm_gpu_cleanup(struct msm_gpu *gpu) in msm_gpu_cleanup() argument
987 DBG("%s", gpu->name); in msm_gpu_cleanup()
989 WARN_ON(!list_empty(&gpu->active_list)); in msm_gpu_cleanup()
991 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { in msm_gpu_cleanup()
992 msm_ringbuffer_destroy(gpu->rb[i]); in msm_gpu_cleanup()
993 gpu->rb[i] = NULL; in msm_gpu_cleanup()
996 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false); in msm_gpu_cleanup()
998 if (!IS_ERR_OR_NULL(gpu->aspace)) { in msm_gpu_cleanup()
999 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu, in msm_gpu_cleanup()
1001 msm_gem_address_space_put(gpu->aspace); in msm_gpu_cleanup()