Lines Matching refs:fb_location
1154 uint64_t fb_location; in dce4_crtc_do_set_base() local
1184 fb_location = radeon_bo_gpu_offset(rbo); in dce4_crtc_do_set_base()
1186 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); in dce4_crtc_do_set_base()
1397 upper_32_bits(fb_location)); in dce4_crtc_do_set_base()
1399 upper_32_bits(fb_location)); in dce4_crtc_do_set_base()
1401 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); in dce4_crtc_do_set_base()
1403 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); in dce4_crtc_do_set_base()
1476 uint64_t fb_location; in avivo_crtc_do_set_base() local
1505 fb_location = radeon_bo_gpu_offset(rbo); in avivo_crtc_do_set_base()
1507 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); in avivo_crtc_do_set_base()
1613 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1614 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1616 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1617 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1621 (u32) fb_location); in avivo_crtc_do_set_base()
1623 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base()