Lines Matching refs:train_set
258 u8 train_set[4]) in dp_get_adjust_train()
290 train_set[lane] = v | p; in dp_get_adjust_train()
548 u8 train_set[4]; member
560 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
564 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
675 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
699 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
707 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
716 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
719 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
728 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_cr()
729 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in radeon_dp_link_train_cr()
768 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_ce()
779 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_ce()
780 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in radeon_dp_link_train_ce()