2644 	pi->dpm_level_enable_mask.pcie_dpm_enable_mask =  in ci_populate_smc_link_level()
3305 	pi->dpm_level_enable_mask.sclk_dpm_enable_mask =  in ci_populate_all_graphic_levels()
3359 	pi->dpm_level_enable_mask.mclk_dpm_enable_mask =  in ci_populate_all_memory_levels()
3823 		if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {  in ci_upload_dpm_level_enable_mask()
3826 								   pi->dpm_level_enable_mask.sclk_dpm_enable_mask);  in ci_upload_dpm_level_enable_mask()
3833 		if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {  in ci_upload_dpm_level_enable_mask()
3836 								   pi->dpm_level_enable_mask.mclk_dpm_enable_mask);  in ci_upload_dpm_level_enable_mask()
3843 		if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {  in ci_upload_dpm_level_enable_mask()
3846 								   pi->dpm_level_enable_mask.pcie_dpm_enable_mask);  in ci_upload_dpm_level_enable_mask()
3943 		pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;  in ci_enable_uvd_dpm()
3947 				pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;  in ci_enable_uvd_dpm()
3956 						  pi->dpm_level_enable_mask.uvd_dpm_enable_mask);  in ci_enable_uvd_dpm()
3960 			pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;  in ci_enable_uvd_dpm()
3963 							  pi->dpm_level_enable_mask.mclk_dpm_enable_mask);  in ci_enable_uvd_dpm()
3968 			pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;  in ci_enable_uvd_dpm()
3971 							  pi->dpm_level_enable_mask.mclk_dpm_enable_mask);  in ci_enable_uvd_dpm()
3992 		pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;  in ci_enable_vce_dpm()
3995 				pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;  in ci_enable_vce_dpm()
4004 						  pi->dpm_level_enable_mask.vce_dpm_enable_mask);  in ci_enable_vce_dpm()
4025 		pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4028 				pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4037 						  pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4056 		pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4059 				pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4068 						  pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4178 	pi->dpm_level_enable_mask.sclk_dpm_enable_mask =  in ci_generate_dpm_level_enable_mask()
4180 	pi->dpm_level_enable_mask.mclk_dpm_enable_mask =  in ci_generate_dpm_level_enable_mask()
4183 		pi->dpm_level_enable_mask.mclk_dpm_enable_mask;  in ci_generate_dpm_level_enable_mask()
4185 		if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)  in ci_generate_dpm_level_enable_mask()
4186 			pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;  in ci_generate_dpm_level_enable_mask()
4188 	pi->dpm_level_enable_mask.pcie_dpm_enable_mask =  in ci_generate_dpm_level_enable_mask()
4215 		    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4217 			tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;  in ci_dpm_force_performance_level()
4234 		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4236 			tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;  in ci_dpm_force_performance_level()
4253 		    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4255 			tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;  in ci_dpm_force_performance_level()
4273 		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4275 							     pi->dpm_level_enable_mask.sclk_dpm_enable_mask);  in ci_dpm_force_performance_level()
4288 		    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4290 							     pi->dpm_level_enable_mask.mclk_dpm_enable_mask);  in ci_dpm_force_performance_level()
4303 		    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4305 							     pi->dpm_level_enable_mask.pcie_dpm_enable_mask);  in ci_dpm_force_performance_level()