7066 	cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7067 	cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7068 	cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7069 	cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7070 	cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7071 	cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7072 	cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7073 	cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7078 		cp_int_cntl |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7086 				cp_m1p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7089 				cp_m1p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7092 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7095 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7104 				cp_m2p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7107 				cp_m2p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7110 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7113 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7129 				cp_m1p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7132 				cp_m1p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7135 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7138 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7147 				cp_m2p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7150 				cp_m2p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7153 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7156 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()