Lines Matching refs:radeon_ring_write
3478 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3479 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_test()
3480 radeon_ring_write(ring, 0xDEADBEEF); in cik_ring_test()
3534 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3535 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in cik_hdp_flush_cp_ring_emit()
3538 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2); in cik_hdp_flush_cp_ring_emit()
3539 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2); in cik_hdp_flush_cp_ring_emit()
3540 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3541 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3542 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_hdp_flush_cp_ring_emit()
3563 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3564 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3568 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3569 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in cik_fence_gfx_ring_emit()
3571 radeon_ring_write(ring, fence->seq - 1); in cik_fence_gfx_ring_emit()
3572 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3575 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3576 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3580 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3581 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()
3582 radeon_ring_write(ring, fence->seq); in cik_fence_gfx_ring_emit()
3583 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3602 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
3603 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_compute_ring_emit()
3607 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
3608 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_compute_ring_emit()
3609 radeon_ring_write(ring, upper_32_bits(addr)); in cik_fence_compute_ring_emit()
3610 radeon_ring_write(ring, fence->seq); in cik_fence_compute_ring_emit()
3611 radeon_ring_write(ring, 0); in cik_fence_compute_ring_emit()
3633 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
3634 radeon_ring_write(ring, lower_32_bits(addr)); in cik_semaphore_ring_emit()
3635 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); in cik_semaphore_ring_emit()
3639 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
3640 radeon_ring_write(ring, 0x0); in cik_semaphore_ring_emit()
3694 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
3695 radeon_ring_write(ring, control); in cik_copy_cpdma()
3696 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_cpdma()
3697 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_cpdma()
3698 radeon_ring_write(ring, lower_32_bits(dst_offset)); in cik_copy_cpdma()
3699 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_cpdma()
3700 radeon_ring_write(ring, cur_size_in_bytes); in cik_copy_cpdma()
3741 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
3742 radeon_ring_write(ring, 0); in cik_ring_ib_execute()
3749 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_ib_execute()
3750 radeon_ring_write(ring, ((ring->rptr_save_reg - in cik_ring_ib_execute()
3752 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
3755 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_ring_ib_execute()
3756 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()
3757 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_ring_ib_execute()
3758 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_ring_ib_execute()
3759 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
3767 radeon_ring_write(ring, header); in cik_ring_ib_execute()
3768 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC)); in cik_ring_ib_execute()
3769 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in cik_ring_ib_execute()
3770 radeon_ring_write(ring, control); in cik_ring_ib_execute()
4004 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start()
4005 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in cik_cp_gfx_start()
4006 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4007 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4010 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4011 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
4013 radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in cik_cp_gfx_start()
4014 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4015 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4018 radeon_ring_write(ring, cik_default_state[i]); in cik_cp_gfx_start()
4020 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4021 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()
4024 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_cp_gfx_start()
4025 radeon_ring_write(ring, 0); in cik_cp_gfx_start()
4027 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_cp_gfx_start()
4028 radeon_ring_write(ring, 0x00000316); in cik_cp_gfx_start()
4029 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in cik_cp_gfx_start()
4030 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in cik_cp_gfx_start()
5697 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
5698 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
5701 radeon_ring_write(ring, in cik_vm_flush()
5704 radeon_ring_write(ring, in cik_vm_flush()
5707 radeon_ring_write(ring, 0); in cik_vm_flush()
5708 radeon_ring_write(ring, pd_addr >> 12); in cik_vm_flush()
5711 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
5712 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
5714 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
5715 radeon_ring_write(ring, 0); in cik_vm_flush()
5716 radeon_ring_write(ring, VMID(vm_id)); in cik_vm_flush()
5718 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); in cik_vm_flush()
5719 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
5721 radeon_ring_write(ring, SH_MEM_BASES >> 2); in cik_vm_flush()
5722 radeon_ring_write(ring, 0); in cik_vm_flush()
5724 radeon_ring_write(ring, 0); /* SH_MEM_BASES */ in cik_vm_flush()
5725 radeon_ring_write(ring, SH_MEM_CONFIG_GFX_DEFAULT); /* SH_MEM_CONFIG */ in cik_vm_flush()
5726 radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ in cik_vm_flush()
5727 radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ in cik_vm_flush()
5729 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
5730 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
5732 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
5733 radeon_ring_write(ring, 0); in cik_vm_flush()
5734 radeon_ring_write(ring, VMID(0)); in cik_vm_flush()
5740 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
5741 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
5743 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
5744 radeon_ring_write(ring, 0); in cik_vm_flush()
5745 radeon_ring_write(ring, 1 << vm_id); in cik_vm_flush()
5748 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_vm_flush()
5749 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in cik_vm_flush()
5752 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
5753 radeon_ring_write(ring, 0); in cik_vm_flush()
5754 radeon_ring_write(ring, 0); /* ref */ in cik_vm_flush()
5755 radeon_ring_write(ring, 0); /* mask */ in cik_vm_flush()
5756 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_vm_flush()
5761 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_vm_flush()
5762 radeon_ring_write(ring, 0x0); in cik_vm_flush()