2804 	u64 src_offset, dst_offset, dst2_offset;  in evergreen_dma_cs_parse()  local
2869 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2870 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2873 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2875 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2894 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2895 					src_offset <<= 8;  in evergreen_dma_cs_parse()
2904 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
2905 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2913 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2915 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2928 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2929 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2932 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2934 							src_offset + count, radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2974 				src_offset = radeon_get_ib_value(p, idx+3);  in evergreen_dma_cs_parse()
2975 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2976 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2978 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3014 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3015 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3016 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3018 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3076 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3077 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3078 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3080 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3105 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3106 					src_offset <<= 8;  in evergreen_dma_cs_parse()
3115 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3116 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3124 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3126 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3163 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3164 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3165 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3167 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()