1748 	u32 reset_mask = 0;  in cayman_gpu_check_soft_reset()  local
1759 		reset_mask |= RADEON_RESET_GFX;  in cayman_gpu_check_soft_reset()
1763 		reset_mask |= RADEON_RESET_CP;  in cayman_gpu_check_soft_reset()
1766 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in cayman_gpu_check_soft_reset()
1771 		reset_mask |= RADEON_RESET_DMA;  in cayman_gpu_check_soft_reset()
1776 		reset_mask |= RADEON_RESET_DMA1;  in cayman_gpu_check_soft_reset()
1781 		reset_mask |= RADEON_RESET_DMA;  in cayman_gpu_check_soft_reset()
1784 		reset_mask |= RADEON_RESET_DMA1;  in cayman_gpu_check_soft_reset()
1789 		reset_mask |= RADEON_RESET_RLC;  in cayman_gpu_check_soft_reset()
1792 		reset_mask |= RADEON_RESET_IH;  in cayman_gpu_check_soft_reset()
1795 		reset_mask |= RADEON_RESET_SEM;  in cayman_gpu_check_soft_reset()
1798 		reset_mask |= RADEON_RESET_GRBM;  in cayman_gpu_check_soft_reset()
1801 		reset_mask |= RADEON_RESET_VMC;  in cayman_gpu_check_soft_reset()
1805 		reset_mask |= RADEON_RESET_MC;  in cayman_gpu_check_soft_reset()
1808 		reset_mask |= RADEON_RESET_DISPLAY;  in cayman_gpu_check_soft_reset()
1813 		reset_mask |= RADEON_RESET_VMC;  in cayman_gpu_check_soft_reset()
1816 	if (reset_mask & RADEON_RESET_MC) {  in cayman_gpu_check_soft_reset()
1817 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in cayman_gpu_check_soft_reset()
1818 		reset_mask &= ~RADEON_RESET_MC;  in cayman_gpu_check_soft_reset()
1821 	return reset_mask;  in cayman_gpu_check_soft_reset()
1824 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in cayman_gpu_soft_reset()  argument
1830 	if (reset_mask == 0)  in cayman_gpu_soft_reset()
1833 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in cayman_gpu_soft_reset()
1848 	if (reset_mask & RADEON_RESET_DMA) {  in cayman_gpu_soft_reset()
1855 	if (reset_mask & RADEON_RESET_DMA1) {  in cayman_gpu_soft_reset()
1869 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in cayman_gpu_soft_reset()
1884 	if (reset_mask & RADEON_RESET_CP) {  in cayman_gpu_soft_reset()
1890 	if (reset_mask & RADEON_RESET_DMA)  in cayman_gpu_soft_reset()
1893 	if (reset_mask & RADEON_RESET_DMA1)  in cayman_gpu_soft_reset()
1896 	if (reset_mask & RADEON_RESET_DISPLAY)  in cayman_gpu_soft_reset()
1899 	if (reset_mask & RADEON_RESET_RLC)  in cayman_gpu_soft_reset()
1902 	if (reset_mask & RADEON_RESET_SEM)  in cayman_gpu_soft_reset()
1905 	if (reset_mask & RADEON_RESET_IH)  in cayman_gpu_soft_reset()
1908 	if (reset_mask & RADEON_RESET_GRBM)  in cayman_gpu_soft_reset()
1911 	if (reset_mask & RADEON_RESET_VMC)  in cayman_gpu_soft_reset()
1915 		if (reset_mask & RADEON_RESET_MC)  in cayman_gpu_soft_reset()
1958 	u32 reset_mask;  in cayman_asic_reset()  local
1965 	reset_mask = cayman_gpu_check_soft_reset(rdev);  in cayman_asic_reset()
1967 	if (reset_mask)  in cayman_asic_reset()
1970 	cayman_gpu_soft_reset(rdev, reset_mask);  in cayman_asic_reset()
1972 	reset_mask = cayman_gpu_check_soft_reset(rdev);  in cayman_asic_reset()
1974 	if (reset_mask)  in cayman_asic_reset()
1993 	u32 reset_mask = cayman_gpu_check_soft_reset(rdev);  in cayman_gfx_is_lockup()  local
1995 	if (!(reset_mask & (RADEON_RESET_GFX |  in cayman_gfx_is_lockup()