Lines Matching refs:dpm
730 struct ni_power_info *pi = rdev->pm.dpm.priv; in ni_get_pi()
797 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ni_apply_state_adjust_rules()
803 if (rdev->pm.dpm.ac_power) in ni_apply_state_adjust_rules()
804 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ni_apply_state_adjust_rules()
806 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ni_apply_state_adjust_rules()
808 if (rdev->pm.dpm.ac_power == false) { in ni_apply_state_adjust_rules()
875 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ni_apply_state_adjust_rules()
878 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ni_apply_state_adjust_rules()
881 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ni_apply_state_adjust_rules()
884 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in ni_apply_state_adjust_rules()
898 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in ni_apply_state_adjust_rules()
901 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) in ni_apply_state_adjust_rules()
1014 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ni_patch_dependency_tables_based_on_leakage()
1017 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ni_patch_dependency_tables_based_on_leakage()
1077 rdev->pm.dpm.forced_level = level; in ni_dpm_force_performance_level()
1230 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in ni_program_response_times()
1231 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; in ni_program_response_times()
1348 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries && in ni_get_std_voltage_value()
1349 ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)) in ni_get_std_voltage_value()
1350 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in ni_get_std_voltage_value()
1440 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) in ni_calculate_adjusted_tdp_limits()
1444 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in ni_calculate_adjusted_tdp_limits()
1445 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit); in ni_calculate_adjusted_tdp_limits()
1447 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in ni_calculate_adjusted_tdp_limits()
1448 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit); in ni_calculate_adjusted_tdp_limits()
1475 rdev->pm.dpm.tdp_adjustment, in ni_populate_smc_tdp_limits()
1945 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in ni_init_smc_table()
1965 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in ni_init_smc_table()
1968 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in ni_init_smc_table()
1971 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in ni_init_smc_table()
2478 rdev->pm.dpm.tdp_adjustment, in ni_populate_power_containment_values()
2553 if (rdev->pm.dpm.sq_ramping_threshold == 0) in ni_populate_sq_ramping_values()
2575 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in ni_populate_sq_ramping_values()
3098 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ni_init_simplified_leakage_table()
3165 ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage; in ni_initialize_smc_cac_tables()
3589 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ni_dpm_enable()
3707 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ni_dpm_disable()
3743 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in ni_power_control_set_level()
3768 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in ni_dpm_pre_set_power_state()
3915 rdev->pm.dpm.boot_ps = rps; in ni_parse_pplib_non_clock_info()
3917 rdev->pm.dpm.uvd_ps = rps; in ni_parse_pplib_non_clock_info()
3978 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in ni_parse_pplib_clock_info()
3979 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in ni_parse_pplib_clock_info()
3980 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in ni_parse_pplib_clock_info()
3981 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in ni_parse_pplib_clock_info()
4003 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates, in ni_parse_power_table()
4006 if (!rdev->pm.dpm.ps) in ni_parse_power_table()
4023 kfree(rdev->pm.dpm.ps); in ni_parse_power_table()
4026 rdev->pm.dpm.ps[i].ps_priv = ps; in ni_parse_power_table()
4027 ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in ni_parse_power_table()
4037 &rdev->pm.dpm.ps[i], j, in ni_parse_power_table()
4042 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; in ni_parse_power_table()
4057 rdev->pm.dpm.priv = ni_pi; in ni_dpm_init()
4080 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in ni_dpm_init()
4084 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in ni_dpm_init()
4088 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in ni_dpm_init()
4089 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in ni_dpm_init()
4090 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in ni_dpm_init()
4091 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in ni_dpm_init()
4092 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in ni_dpm_init()
4093 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in ni_dpm_init()
4094 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in ni_dpm_init()
4095 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in ni_dpm_init()
4096 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in ni_dpm_init()
4100 if (rdev->pm.dpm.voltage_response_time == 0) in ni_dpm_init()
4101 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in ni_dpm_init()
4102 if (rdev->pm.dpm.backbias_response_time == 0) in ni_dpm_init()
4103 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in ni_dpm_init()
4197 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3; in ni_dpm_init()
4198 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ni_dpm_init()
4199 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; in ni_dpm_init()
4200 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk); in ni_dpm_init()
4201 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk; in ni_dpm_init()
4202 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ni_dpm_init()
4203 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in ni_dpm_init()
4204 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500; in ni_dpm_init()
4261 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ni_dpm_init()
4262 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ni_dpm_init()
4263 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ni_dpm_init()
4264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ni_dpm_init()
4273 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in ni_dpm_fini()
4274 kfree(rdev->pm.dpm.ps[i].ps_priv); in ni_dpm_fini()
4276 kfree(rdev->pm.dpm.ps); in ni_dpm_fini()
4277 kfree(rdev->pm.dpm.priv); in ni_dpm_fini()
4278 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in ni_dpm_fini()