Lines Matching refs:rdev
61 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) in rv370_pcie_rreg() argument
66 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); in rv370_pcie_rreg()
67 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); in rv370_pcie_rreg()
69 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); in rv370_pcie_rreg()
73 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) in rv370_pcie_wreg() argument
77 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); in rv370_pcie_wreg()
78 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); in rv370_pcie_wreg()
80 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); in rv370_pcie_wreg()
86 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
88 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) in rv370_pcie_gart_tlb_flush() argument
120 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, in rv370_pcie_gart_set_page() argument
123 void __iomem *ptr = rdev->gart.ptr; in rv370_pcie_gart_set_page()
131 int rv370_pcie_gart_init(struct radeon_device *rdev) in rv370_pcie_gart_init() argument
135 if (rdev->gart.robj) { in rv370_pcie_gart_init()
140 r = radeon_gart_init(rdev); in rv370_pcie_gart_init()
143 r = rv370_debugfs_pcie_gart_info_init(rdev); in rv370_pcie_gart_init()
146 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rv370_pcie_gart_init()
147 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in rv370_pcie_gart_init()
148 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in rv370_pcie_gart_init()
149 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in rv370_pcie_gart_init()
150 return radeon_gart_table_vram_alloc(rdev); in rv370_pcie_gart_init()
153 int rv370_pcie_gart_enable(struct radeon_device *rdev) in rv370_pcie_gart_enable() argument
159 if (rdev->gart.robj == NULL) { in rv370_pcie_gart_enable()
160 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rv370_pcie_gart_enable()
163 r = radeon_gart_table_vram_pin(rdev); in rv370_pcie_gart_enable()
169 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); in rv370_pcie_gart_enable()
170 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; in rv370_pcie_gart_enable()
174 table_addr = rdev->gart.table_addr; in rv370_pcie_gart_enable()
177 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); in rv370_pcie_gart_enable()
185 rv370_pcie_gart_tlb_flush(rdev); in rv370_pcie_gart_enable()
187 (unsigned)(rdev->mc.gtt_size >> 20), in rv370_pcie_gart_enable()
189 rdev->gart.ready = true; in rv370_pcie_gart_enable()
193 void rv370_pcie_gart_disable(struct radeon_device *rdev) in rv370_pcie_gart_disable() argument
204 radeon_gart_table_vram_unpin(rdev); in rv370_pcie_gart_disable()
207 void rv370_pcie_gart_fini(struct radeon_device *rdev) in rv370_pcie_gart_fini() argument
209 radeon_gart_fini(rdev); in rv370_pcie_gart_fini()
210 rv370_pcie_gart_disable(rdev); in rv370_pcie_gart_fini()
211 radeon_gart_table_vram_free(rdev); in rv370_pcie_gart_fini()
214 void r300_fence_ring_emit(struct radeon_device *rdev, in r300_fence_ring_emit() argument
217 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r300_fence_ring_emit()
237 radeon_ring_write(ring, rdev->config.r300.hdp_cntl | in r300_fence_ring_emit()
240 radeon_ring_write(ring, rdev->config.r300.hdp_cntl); in r300_fence_ring_emit()
242 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r300_fence_ring_emit()
248 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) in r300_ring_start() argument
255 switch(rdev->num_gb_pipes) { in r300_ring_start()
271 r = radeon_ring_lock(rdev, ring, 64); in r300_ring_start()
335 radeon_ring_unlock_commit(rdev, ring, false); in r300_ring_start()
338 static void r300_errata(struct radeon_device *rdev) in r300_errata() argument
340 rdev->pll_errata = 0; in r300_errata()
342 if (rdev->family == CHIP_R300 && in r300_errata()
344 rdev->pll_errata |= CHIP_ERRATA_R300_CG; in r300_errata()
348 int r300_mc_wait_for_idle(struct radeon_device *rdev) in r300_mc_wait_for_idle() argument
353 for (i = 0; i < rdev->usec_timeout; i++) { in r300_mc_wait_for_idle()
364 static void r300_gpu_init(struct radeon_device *rdev) in r300_gpu_init() argument
368 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || in r300_gpu_init()
369 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { in r300_gpu_init()
371 rdev->num_gb_pipes = 2; in r300_gpu_init()
374 rdev->num_gb_pipes = 1; in r300_gpu_init()
376 rdev->num_z_pipes = 1; in r300_gpu_init()
378 switch (rdev->num_gb_pipes) { in r300_gpu_init()
395 if (r100_gui_wait_for_idle(rdev)) { in r300_gpu_init()
406 if (r100_gui_wait_for_idle(rdev)) { in r300_gpu_init()
409 if (r300_mc_wait_for_idle(rdev)) { in r300_gpu_init()
413 rdev->num_gb_pipes, rdev->num_z_pipes); in r300_gpu_init()
416 int r300_asic_reset(struct radeon_device *rdev, bool hard) in r300_asic_reset() argument
426 r100_mc_stop(rdev, &save); in r300_asic_reset()
428 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r300_asic_reset()
437 pci_save_state(rdev->pdev); in r300_asic_reset()
439 r100_bm_disable(rdev); in r300_asic_reset()
447 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r300_asic_reset()
459 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r300_asic_reset()
461 pci_restore_state(rdev->pdev); in r300_asic_reset()
462 r100_enable_bm(rdev); in r300_asic_reset()
465 dev_err(rdev->dev, "failed to reset GPU\n"); in r300_asic_reset()
468 dev_info(rdev->dev, "GPU reset succeed\n"); in r300_asic_reset()
469 r100_mc_resume(rdev, &save); in r300_asic_reset()
476 void r300_mc_init(struct radeon_device *rdev) in r300_mc_init() argument
482 rdev->mc.vram_is_ddr = true; in r300_mc_init()
486 case 0: rdev->mc.vram_width = 64; break; in r300_mc_init()
487 case 1: rdev->mc.vram_width = 128; break; in r300_mc_init()
488 case 2: rdev->mc.vram_width = 256; break; in r300_mc_init()
489 default: rdev->mc.vram_width = 128; break; in r300_mc_init()
491 r100_vram_init_sizes(rdev); in r300_mc_init()
492 base = rdev->mc.aper_base; in r300_mc_init()
493 if (rdev->flags & RADEON_IS_IGP) in r300_mc_init()
495 radeon_vram_location(rdev, &rdev->mc, base); in r300_mc_init()
496 rdev->mc.gtt_base_align = 0; in r300_mc_init()
497 if (!(rdev->flags & RADEON_IS_AGP)) in r300_mc_init()
498 radeon_gtt_location(rdev, &rdev->mc); in r300_mc_init()
499 radeon_update_bandwidth_info(rdev); in r300_mc_init()
502 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) in rv370_set_pcie_lanes() argument
506 if (rdev->flags & RADEON_IS_IGP) in rv370_set_pcie_lanes()
509 if (!(rdev->flags & RADEON_IS_PCIE)) in rv370_set_pcie_lanes()
561 int rv370_get_pcie_lanes(struct radeon_device *rdev) in rv370_get_pcie_lanes() argument
565 if (rdev->flags & RADEON_IS_IGP) in rv370_get_pcie_lanes()
568 if (!(rdev->flags & RADEON_IS_PCIE)) in rv370_get_pcie_lanes()
597 struct radeon_device *rdev = dev->dev_private; in rv370_debugfs_pcie_gart_info() local
622 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) in rv370_debugfs_pcie_gart_info_init() argument
625 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); in rv370_debugfs_pcie_gart_info_init()
752 if (p->rdev->family < CHIP_RV515) in r300_packet0_check()
759 if (p->rdev->family < CHIP_RV515) { in r300_packet0_check()
768 p->rdev->cmask_filp != p->filp) { in r300_packet0_check()
818 if (p->rdev->family < CHIP_RV515) { in r300_packet0_check()
968 if (p->rdev->family < CHIP_R420) { in r300_packet0_check()
1035 if (p->rdev->family >= CHIP_RV515) { in r300_packet0_check()
1102 if (p->rdev->hyperz_filp != p->filp) { in r300_packet0_check()
1112 if (p->rdev->hyperz_filp != p->filp) { in r300_packet0_check()
1150 if (idx_value && (p->rdev->hyperz_filp != p->filp)) in r300_packet0_check()
1154 if (idx_value && (p->rdev->hyperz_filp != p->filp)) in r300_packet0_check()
1157 if (p->rdev->family >= CHIP_RV350) in r300_packet0_check()
1163 if (p->rdev->family == CHIP_RV530) in r300_packet0_check()
1218 r = r100_cs_track_check(p->rdev, track); in r300_packet3_check()
1233 r = r100_cs_track_check(p->rdev, track); in r300_packet3_check()
1240 r = r100_cs_track_check(p->rdev, track); in r300_packet3_check()
1247 r = r100_cs_track_check(p->rdev, track); in r300_packet3_check()
1254 r = r100_cs_track_check(p->rdev, track); in r300_packet3_check()
1261 r = r100_cs_track_check(p->rdev, track); in r300_packet3_check()
1268 if (p->rdev->hyperz_filp != p->filp) in r300_packet3_check()
1272 if (p->rdev->cmask_filp != p->filp) in r300_packet3_check()
1293 r100_cs_track_clear(p->rdev, track); in r300_cs_parse()
1304 p->rdev->config.r300.reg_safe_bm, in r300_cs_parse()
1305 p->rdev->config.r300.reg_safe_bm_size, in r300_cs_parse()
1324 void r300_set_reg_safe(struct radeon_device *rdev) in r300_set_reg_safe() argument
1326 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; in r300_set_reg_safe()
1327 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); in r300_set_reg_safe()
1330 void r300_mc_program(struct radeon_device *rdev) in r300_mc_program() argument
1335 r = r100_debugfs_mc_info_init(rdev); in r300_mc_program()
1337 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); in r300_mc_program()
1341 r100_mc_stop(rdev, &save); in r300_mc_program()
1342 if (rdev->flags & RADEON_IS_AGP) { in r300_mc_program()
1344 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | in r300_mc_program()
1345 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); in r300_mc_program()
1346 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); in r300_mc_program()
1348 upper_32_bits(rdev->mc.agp_base) & 0xff); in r300_mc_program()
1355 if (r300_mc_wait_for_idle(rdev)) in r300_mc_program()
1359 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in r300_mc_program()
1360 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); in r300_mc_program()
1361 r100_mc_resume(rdev, &save); in r300_mc_program()
1364 void r300_clock_startup(struct radeon_device *rdev) in r300_clock_startup() argument
1369 radeon_legacy_set_clock_gating(rdev, 1); in r300_clock_startup()
1373 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) in r300_clock_startup()
1378 static int r300_startup(struct radeon_device *rdev) in r300_startup() argument
1383 r100_set_common_regs(rdev); in r300_startup()
1385 r300_mc_program(rdev); in r300_startup()
1387 r300_clock_startup(rdev); in r300_startup()
1389 r300_gpu_init(rdev); in r300_startup()
1392 if (rdev->flags & RADEON_IS_PCIE) { in r300_startup()
1393 r = rv370_pcie_gart_enable(rdev); in r300_startup()
1398 if (rdev->family == CHIP_R300 || in r300_startup()
1399 rdev->family == CHIP_R350 || in r300_startup()
1400 rdev->family == CHIP_RV350) in r300_startup()
1401 r100_enable_bm(rdev); in r300_startup()
1403 if (rdev->flags & RADEON_IS_PCI) { in r300_startup()
1404 r = r100_pci_gart_enable(rdev); in r300_startup()
1410 r = radeon_wb_init(rdev); in r300_startup()
1414 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r300_startup()
1416 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r300_startup()
1421 if (!rdev->irq.installed) { in r300_startup()
1422 r = radeon_irq_kms_init(rdev); in r300_startup()
1427 r100_irq_set(rdev); in r300_startup()
1428 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r300_startup()
1430 r = r100_cp_init(rdev, 1024 * 1024); in r300_startup()
1432 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r300_startup()
1436 r = radeon_ib_pool_init(rdev); in r300_startup()
1438 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r300_startup()
1445 int r300_resume(struct radeon_device *rdev) in r300_resume() argument
1450 if (rdev->flags & RADEON_IS_PCIE) in r300_resume()
1451 rv370_pcie_gart_disable(rdev); in r300_resume()
1452 if (rdev->flags & RADEON_IS_PCI) in r300_resume()
1453 r100_pci_gart_disable(rdev); in r300_resume()
1455 r300_clock_startup(rdev); in r300_resume()
1457 if (radeon_asic_reset(rdev)) { in r300_resume()
1458 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r300_resume()
1463 radeon_combios_asic_init(rdev->ddev); in r300_resume()
1465 r300_clock_startup(rdev); in r300_resume()
1467 radeon_surface_init(rdev); in r300_resume()
1469 rdev->accel_working = true; in r300_resume()
1470 r = r300_startup(rdev); in r300_resume()
1472 rdev->accel_working = false; in r300_resume()
1477 int r300_suspend(struct radeon_device *rdev) in r300_suspend() argument
1479 radeon_pm_suspend(rdev); in r300_suspend()
1480 r100_cp_disable(rdev); in r300_suspend()
1481 radeon_wb_disable(rdev); in r300_suspend()
1482 r100_irq_disable(rdev); in r300_suspend()
1483 if (rdev->flags & RADEON_IS_PCIE) in r300_suspend()
1484 rv370_pcie_gart_disable(rdev); in r300_suspend()
1485 if (rdev->flags & RADEON_IS_PCI) in r300_suspend()
1486 r100_pci_gart_disable(rdev); in r300_suspend()
1490 void r300_fini(struct radeon_device *rdev) in r300_fini() argument
1492 radeon_pm_fini(rdev); in r300_fini()
1493 r100_cp_fini(rdev); in r300_fini()
1494 radeon_wb_fini(rdev); in r300_fini()
1495 radeon_ib_pool_fini(rdev); in r300_fini()
1496 radeon_gem_fini(rdev); in r300_fini()
1497 if (rdev->flags & RADEON_IS_PCIE) in r300_fini()
1498 rv370_pcie_gart_fini(rdev); in r300_fini()
1499 if (rdev->flags & RADEON_IS_PCI) in r300_fini()
1500 r100_pci_gart_fini(rdev); in r300_fini()
1501 radeon_agp_fini(rdev); in r300_fini()
1502 radeon_irq_kms_fini(rdev); in r300_fini()
1503 radeon_fence_driver_fini(rdev); in r300_fini()
1504 radeon_bo_fini(rdev); in r300_fini()
1505 radeon_atombios_fini(rdev); in r300_fini()
1506 kfree(rdev->bios); in r300_fini()
1507 rdev->bios = NULL; in r300_fini()
1510 int r300_init(struct radeon_device *rdev) in r300_init() argument
1515 r100_vga_render_disable(rdev); in r300_init()
1517 radeon_scratch_init(rdev); in r300_init()
1519 radeon_surface_init(rdev); in r300_init()
1522 r100_restore_sanity(rdev); in r300_init()
1524 if (!radeon_get_bios(rdev)) { in r300_init()
1525 if (ASIC_IS_AVIVO(rdev)) in r300_init()
1528 if (rdev->is_atom_bios) { in r300_init()
1529 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); in r300_init()
1532 r = radeon_combios_init(rdev); in r300_init()
1537 if (radeon_asic_reset(rdev)) { in r300_init()
1538 dev_warn(rdev->dev, in r300_init()
1544 if (radeon_boot_test_post_card(rdev) == false) in r300_init()
1547 r300_errata(rdev); in r300_init()
1549 radeon_get_clock_info(rdev->ddev); in r300_init()
1551 if (rdev->flags & RADEON_IS_AGP) { in r300_init()
1552 r = radeon_agp_init(rdev); in r300_init()
1554 radeon_agp_disable(rdev); in r300_init()
1558 r300_mc_init(rdev); in r300_init()
1560 r = radeon_fence_driver_init(rdev); in r300_init()
1564 r = radeon_bo_init(rdev); in r300_init()
1567 if (rdev->flags & RADEON_IS_PCIE) { in r300_init()
1568 r = rv370_pcie_gart_init(rdev); in r300_init()
1572 if (rdev->flags & RADEON_IS_PCI) { in r300_init()
1573 r = r100_pci_gart_init(rdev); in r300_init()
1577 r300_set_reg_safe(rdev); in r300_init()
1580 radeon_pm_init(rdev); in r300_init()
1582 rdev->accel_working = true; in r300_init()
1583 r = r300_startup(rdev); in r300_init()
1586 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r300_init()
1587 r100_cp_fini(rdev); in r300_init()
1588 radeon_wb_fini(rdev); in r300_init()
1589 radeon_ib_pool_fini(rdev); in r300_init()
1590 radeon_irq_kms_fini(rdev); in r300_init()
1591 if (rdev->flags & RADEON_IS_PCIE) in r300_init()
1592 rv370_pcie_gart_fini(rdev); in r300_init()
1593 if (rdev->flags & RADEON_IS_PCI) in r300_init()
1594 r100_pci_gart_fini(rdev); in r300_init()
1595 radeon_agp_fini(rdev); in r300_init()
1596 rdev->accel_working = false; in r300_init()