Lines Matching refs:radeon_ring_write
2696 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2697 radeon_ring_write(ring, 0x1); in r600_cp_start()
2699 radeon_ring_write(ring, 0x0); in r600_cp_start()
2700 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2702 radeon_ring_write(ring, 0x3); in r600_cp_start()
2703 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2705 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in r600_cp_start()
2706 radeon_ring_write(ring, 0); in r600_cp_start()
2707 radeon_ring_write(ring, 0); in r600_cp_start()
2841 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2842 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); in r600_ring_test()
2843 radeon_ring_write(ring, 0xDEADBEEF); in r600_ring_test()
2879 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2880 radeon_ring_write(ring, cp_coher_cntl); in r600_fence_ring_emit()
2881 radeon_ring_write(ring, 0xFFFFFFFF); in r600_fence_ring_emit()
2882 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2883 radeon_ring_write(ring, 10); /* poll interval */ in r600_fence_ring_emit()
2885 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2886 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in r600_fence_ring_emit()
2887 radeon_ring_write(ring, lower_32_bits(addr)); in r600_fence_ring_emit()
2888 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
2889 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2890 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2893 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2894 radeon_ring_write(ring, cp_coher_cntl); in r600_fence_ring_emit()
2895 radeon_ring_write(ring, 0xFFFFFFFF); in r600_fence_ring_emit()
2896 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2897 radeon_ring_write(ring, 10); /* poll interval */ in r600_fence_ring_emit()
2898 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2899 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); in r600_fence_ring_emit()
2901 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2902 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_fence_ring_emit()
2903 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); in r600_fence_ring_emit()
2905 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2906 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
2907 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2909 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); in r600_fence_ring_emit()
2910 radeon_ring_write(ring, RB_INT_STAT); in r600_fence_ring_emit()
2936 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2937 radeon_ring_write(ring, lower_32_bits(addr)); in r600_semaphore_ring_emit()
2938 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); in r600_semaphore_ring_emit()
2943 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit()
2944 radeon_ring_write(ring, 0x0); in r600_semaphore_ring_emit()
2990 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
2991 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_copy_cpdma()
2992 radeon_ring_write(ring, WAIT_3D_IDLE_bit); in r600_copy_cpdma()
3001 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); in r600_copy_cpdma()
3002 radeon_ring_write(ring, lower_32_bits(src_offset)); in r600_copy_cpdma()
3003 radeon_ring_write(ring, tmp); in r600_copy_cpdma()
3004 radeon_ring_write(ring, lower_32_bits(dst_offset)); in r600_copy_cpdma()
3005 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in r600_copy_cpdma()
3006 radeon_ring_write(ring, cur_size_in_bytes); in r600_copy_cpdma()
3010 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
3011 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_copy_cpdma()
3012 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); in r600_copy_cpdma()
3376 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_ib_execute()
3377 radeon_ring_write(ring, ((ring->rptr_save_reg - in r600_ring_ib_execute()
3379 radeon_ring_write(ring, next_rptr); in r600_ring_ib_execute()
3382 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in r600_ring_ib_execute()
3383 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in r600_ring_ib_execute()
3384 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); in r600_ring_ib_execute()
3385 radeon_ring_write(ring, next_rptr); in r600_ring_ib_execute()
3386 radeon_ring_write(ring, 0); in r600_ring_ib_execute()
3389 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in r600_ring_ib_execute()
3390 radeon_ring_write(ring, in r600_ring_ib_execute()
3395 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in r600_ring_ib_execute()
3396 radeon_ring_write(ring, ib->length_dw); in r600_ring_ib_execute()