Lines Matching refs:rdev
106 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
109 int r600_mc_wait_for_idle(struct radeon_device *rdev);
110 static void r600_gpu_init(struct radeon_device *rdev);
111 void r600_fini(struct radeon_device *rdev);
112 void r600_irq_disable(struct radeon_device *rdev);
113 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
114 extern int evergreen_rlc_resume(struct radeon_device *rdev);
115 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
120 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) in r600_rcu_rreg() argument
125 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); in r600_rcu_rreg()
128 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); in r600_rcu_rreg()
132 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r600_rcu_wreg() argument
136 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); in r600_rcu_wreg()
139 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); in r600_rcu_wreg()
142 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) in r600_uvd_ctx_rreg() argument
147 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_rreg()
150 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_rreg()
154 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r600_uvd_ctx_wreg() argument
158 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_wreg()
161 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_wreg()
174 int r600_get_allowed_info_register(struct radeon_device *rdev, in r600_get_allowed_info_register() argument
198 u32 r600_get_xclk(struct radeon_device *rdev) in r600_get_xclk() argument
200 return rdev->clock.spll.reference_freq; in r600_get_xclk()
203 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in r600_set_uvd_clocks() argument
217 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
227 if (rdev->clock.spll.reference_freq == 10000) in r600_set_uvd_clocks()
232 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in r600_set_uvd_clocks()
238 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) in r600_set_uvd_clocks()
243 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in r600_set_uvd_clocks()
251 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
279 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
282 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in r600_set_uvd_clocks()
299 struct radeon_device *rdev = dev->dev_private; in dce3_program_fmt() local
350 int rv6xx_get_temp(struct radeon_device *rdev) in rv6xx_get_temp() argument
362 void r600_pm_get_dynpm_state(struct radeon_device *rdev) in r600_pm_get_dynpm_state() argument
366 rdev->pm.dynpm_can_upclock = true; in r600_pm_get_dynpm_state()
367 rdev->pm.dynpm_can_downclock = true; in r600_pm_get_dynpm_state()
370 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { in r600_pm_get_dynpm_state()
373 if (rdev->pm.num_power_states > 2) in r600_pm_get_dynpm_state()
376 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
378 rdev->pm.requested_power_state_index = min_power_state_index; in r600_pm_get_dynpm_state()
379 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
380 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
383 if (rdev->pm.current_power_state_index == min_power_state_index) { in r600_pm_get_dynpm_state()
384 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
385 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
387 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
388 for (i = 0; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
389 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
391 else if (i >= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
392 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
393 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
396 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
401 if (rdev->pm.current_power_state_index == 0) in r600_pm_get_dynpm_state()
402 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
403 rdev->pm.num_power_states - 1; in r600_pm_get_dynpm_state()
405 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
406 rdev->pm.current_power_state_index - 1; in r600_pm_get_dynpm_state()
409 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
411 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
412 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
413 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
415 rdev->pm.requested_power_state_index++; in r600_pm_get_dynpm_state()
419 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { in r600_pm_get_dynpm_state()
420 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
421 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
423 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
424 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { in r600_pm_get_dynpm_state()
425 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
427 else if (i <= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
428 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
429 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
432 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
437 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
438 rdev->pm.current_power_state_index + 1; in r600_pm_get_dynpm_state()
440 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
443 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
444 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
445 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
456 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
457 rdev->pm.requested_power_state_index = -1; in r600_pm_get_dynpm_state()
459 for (i = 1; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
460 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
462 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || in r600_pm_get_dynpm_state()
463 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { in r600_pm_get_dynpm_state()
464 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
469 if (rdev->pm.requested_power_state_index == -1) in r600_pm_get_dynpm_state()
470 rdev->pm.requested_power_state_index = 0; in r600_pm_get_dynpm_state()
472 rdev->pm.requested_power_state_index = 1; in r600_pm_get_dynpm_state()
474 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
476 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
477 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
480 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
481 if (rdev->pm.current_clock_mode_index == 0) { in r600_pm_get_dynpm_state()
482 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
483 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
485 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
486 rdev->pm.current_clock_mode_index - 1; in r600_pm_get_dynpm_state()
488 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
489 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
492 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
493 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
494 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
496 rdev->pm.requested_clock_mode_index++; in r600_pm_get_dynpm_state()
500 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
501 if (rdev->pm.current_clock_mode_index == in r600_pm_get_dynpm_state()
502 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { in r600_pm_get_dynpm_state()
503 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; in r600_pm_get_dynpm_state()
504 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
506 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
507 rdev->pm.current_clock_mode_index + 1; in r600_pm_get_dynpm_state()
509 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
510 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; in r600_pm_get_dynpm_state()
511 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
515 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
516 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
517 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
527 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
528 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r600_pm_get_dynpm_state()
529 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
530 clock_info[rdev->pm.requested_clock_mode_index].mclk, in r600_pm_get_dynpm_state()
531 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
535 void rs780_pm_init_profile(struct radeon_device *rdev) in rs780_pm_init_profile() argument
537 if (rdev->pm.num_power_states == 2) { in rs780_pm_init_profile()
539 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
540 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
541 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
542 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
544 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
545 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
546 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
547 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
549 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
550 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
551 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
552 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
554 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
555 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
556 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
557 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
559 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
560 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
561 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
562 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
569 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
573 } else if (rdev->pm.num_power_states == 3) { in rs780_pm_init_profile()
575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
580 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
585 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
590 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
595 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
600 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
605 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
611 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
616 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
621 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
626 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
631 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
636 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
641 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
648 void r600_pm_init_profile(struct radeon_device *rdev) in r600_pm_init_profile() argument
652 if (rdev->family == CHIP_R600) { in r600_pm_init_profile()
655 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
656 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
657 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
658 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
660 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
661 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
662 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
663 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
665 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
666 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
667 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
668 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
670 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
672 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
673 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
675 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
676 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
680 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
681 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
685 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
686 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
687 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
690 if (rdev->pm.num_power_states < 4) { in r600_pm_init_profile()
692 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
693 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
694 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
695 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
697 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
698 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
699 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
700 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
702 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
703 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
704 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
705 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
707 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
708 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
709 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
710 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
712 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
713 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
714 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
715 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
717 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
718 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
719 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
720 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
722 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
723 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
724 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
725 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
728 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
729 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
730 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
731 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
733 if (rdev->flags & RADEON_IS_MOBILITY) in r600_pm_init_profile()
734 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); in r600_pm_init_profile()
736 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in r600_pm_init_profile()
737 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
738 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
739 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
740 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
742 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
743 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
744 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
745 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
747 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in r600_pm_init_profile()
748 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
749 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
750 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
751 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
753 if (rdev->flags & RADEON_IS_MOBILITY) in r600_pm_init_profile()
754 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); in r600_pm_init_profile()
756 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); in r600_pm_init_profile()
757 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
758 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
759 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
760 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
762 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
763 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
764 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
765 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
767 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); in r600_pm_init_profile()
768 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
769 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
770 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
771 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
776 void r600_pm_misc(struct radeon_device *rdev) in r600_pm_misc() argument
778 int req_ps_idx = rdev->pm.requested_power_state_index; in r600_pm_misc()
779 int req_cm_idx = rdev->pm.requested_clock_mode_index; in r600_pm_misc()
780 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in r600_pm_misc()
787 if (voltage->voltage != rdev->pm.current_vddc) { in r600_pm_misc()
788 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in r600_pm_misc()
789 rdev->pm.current_vddc = voltage->voltage; in r600_pm_misc()
795 bool r600_gui_idle(struct radeon_device *rdev) in r600_gui_idle() argument
804 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) in r600_hpd_sense() argument
808 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_sense()
859 void r600_hpd_set_polarity(struct radeon_device *rdev, in r600_hpd_set_polarity() argument
863 bool connected = r600_hpd_sense(rdev, hpd); in r600_hpd_set_polarity()
865 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_set_polarity()
951 void r600_hpd_init(struct radeon_device *rdev) in r600_hpd_init() argument
953 struct drm_device *dev = rdev->ddev; in r600_hpd_init()
968 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_init()
970 if (ASIC_IS_DCE32(rdev)) in r600_hpd_init()
1013 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in r600_hpd_init()
1015 radeon_irq_kms_enable_hpd(rdev, enable); in r600_hpd_init()
1018 void r600_hpd_fini(struct radeon_device *rdev) in r600_hpd_fini() argument
1020 struct drm_device *dev = rdev->ddev; in r600_hpd_fini()
1026 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_fini()
1068 radeon_irq_kms_disable_hpd(rdev, disable); in r600_hpd_fini()
1074 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) in r600_pcie_gart_tlb_flush() argument
1080 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && in r600_pcie_gart_tlb_flush()
1081 !(rdev->flags & RADEON_IS_AGP)) { in r600_pcie_gart_tlb_flush()
1082 void __iomem *ptr = (void *)rdev->gart.ptr; in r600_pcie_gart_tlb_flush()
1095 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_tlb_flush()
1096 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); in r600_pcie_gart_tlb_flush()
1098 for (i = 0; i < rdev->usec_timeout; i++) { in r600_pcie_gart_tlb_flush()
1113 int r600_pcie_gart_init(struct radeon_device *rdev) in r600_pcie_gart_init() argument
1117 if (rdev->gart.robj) { in r600_pcie_gart_init()
1122 r = radeon_gart_init(rdev); in r600_pcie_gart_init()
1125 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in r600_pcie_gart_init()
1126 return radeon_gart_table_vram_alloc(rdev); in r600_pcie_gart_init()
1129 static int r600_pcie_gart_enable(struct radeon_device *rdev) in r600_pcie_gart_enable() argument
1134 if (rdev->gart.robj == NULL) { in r600_pcie_gart_enable()
1135 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in r600_pcie_gart_enable()
1138 r = radeon_gart_table_vram_pin(rdev); in r600_pcie_gart_enable()
1169 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_enable()
1170 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in r600_pcie_gart_enable()
1171 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
1175 (u32)(rdev->dummy_page.addr >> 12)); in r600_pcie_gart_enable()
1179 r600_pcie_gart_tlb_flush(rdev); in r600_pcie_gart_enable()
1181 (unsigned)(rdev->mc.gtt_size >> 20), in r600_pcie_gart_enable()
1182 (unsigned long long)rdev->gart.table_addr); in r600_pcie_gart_enable()
1183 rdev->gart.ready = true; in r600_pcie_gart_enable()
1187 static void r600_pcie_gart_disable(struct radeon_device *rdev) in r600_pcie_gart_disable() argument
1219 radeon_gart_table_vram_unpin(rdev); in r600_pcie_gart_disable()
1222 static void r600_pcie_gart_fini(struct radeon_device *rdev) in r600_pcie_gart_fini() argument
1224 radeon_gart_fini(rdev); in r600_pcie_gart_fini()
1225 r600_pcie_gart_disable(rdev); in r600_pcie_gart_fini()
1226 radeon_gart_table_vram_free(rdev); in r600_pcie_gart_fini()
1229 static void r600_agp_enable(struct radeon_device *rdev) in r600_agp_enable() argument
1263 int r600_mc_wait_for_idle(struct radeon_device *rdev) in r600_mc_wait_for_idle() argument
1268 for (i = 0; i < rdev->usec_timeout; i++) { in r600_mc_wait_for_idle()
1278 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) in rs780_mc_rreg() argument
1283 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs780_mc_rreg()
1287 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs780_mc_rreg()
1291 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) in rs780_mc_wreg() argument
1295 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs780_mc_wreg()
1300 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs780_mc_wreg()
1303 static void r600_mc_program(struct radeon_device *rdev) in r600_mc_program() argument
1319 rv515_mc_stop(rdev, &save); in r600_mc_program()
1320 if (r600_mc_wait_for_idle(rdev)) { in r600_mc_program()
1321 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1326 if (rdev->flags & RADEON_IS_AGP) { in r600_mc_program()
1327 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1330 rdev->mc.vram_start >> 12); in r600_mc_program()
1332 rdev->mc.gtt_end >> 12); in r600_mc_program()
1336 rdev->mc.gtt_start >> 12); in r600_mc_program()
1338 rdev->mc.vram_end >> 12); in r600_mc_program()
1341 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1342 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); in r600_mc_program()
1344 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in r600_mc_program()
1345 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in r600_mc_program()
1346 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1348 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1351 if (rdev->flags & RADEON_IS_AGP) { in r600_mc_program()
1352 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); in r600_mc_program()
1353 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); in r600_mc_program()
1354 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in r600_mc_program()
1360 if (r600_mc_wait_for_idle(rdev)) { in r600_mc_program()
1361 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1363 rv515_mc_resume(rdev, &save); in r600_mc_program()
1366 rv515_vga_render_disable(rdev); in r600_mc_program()
1390 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) in r600_vram_gtt_location() argument
1396 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1400 if (rdev->flags & RADEON_IS_AGP) { in r600_vram_gtt_location()
1405 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1412 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1419 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", in r600_vram_gtt_location()
1424 if (rdev->flags & RADEON_IS_IGP) { in r600_vram_gtt_location()
1428 radeon_vram_location(rdev, &rdev->mc, base); in r600_vram_gtt_location()
1429 rdev->mc.gtt_base_align = 0; in r600_vram_gtt_location()
1430 radeon_gtt_location(rdev, mc); in r600_vram_gtt_location()
1434 static int r600_mc_init(struct radeon_device *rdev) in r600_mc_init() argument
1442 rdev->mc.vram_is_ddr = true; in r600_mc_init()
1467 rdev->mc.vram_width = numchan * chansize; in r600_mc_init()
1469 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r600_mc_init()
1470 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r600_mc_init()
1472 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1473 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1474 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r600_mc_init()
1475 r600_vram_gtt_location(rdev, &rdev->mc); in r600_mc_init()
1477 if (rdev->flags & RADEON_IS_IGP) { in r600_mc_init()
1478 rs690_pm_info(rdev); in r600_mc_init()
1479 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in r600_mc_init()
1481 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { in r600_mc_init()
1483 rdev->fastfb_working = false; in r600_mc_init()
1488 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) in r600_mc_init()
1494 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { in r600_mc_init()
1496 (unsigned long long)rdev->mc.aper_base, k8_addr); in r600_mc_init()
1497 rdev->mc.aper_base = (resource_size_t)k8_addr; in r600_mc_init()
1498 rdev->fastfb_working = true; in r600_mc_init()
1504 radeon_update_bandwidth_info(rdev); in r600_mc_init()
1508 int r600_vram_scratch_init(struct radeon_device *rdev) in r600_vram_scratch_init() argument
1512 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_init()
1513 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, in r600_vram_scratch_init()
1515 0, NULL, NULL, &rdev->vram_scratch.robj); in r600_vram_scratch_init()
1521 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_init()
1524 r = radeon_bo_pin(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1525 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); in r600_vram_scratch_init()
1527 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1530 r = radeon_bo_kmap(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1531 (void **)&rdev->vram_scratch.ptr); in r600_vram_scratch_init()
1533 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1534 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1539 void r600_vram_scratch_fini(struct radeon_device *rdev) in r600_vram_scratch_fini() argument
1543 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_fini()
1546 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_fini()
1548 radeon_bo_kunmap(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1549 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1550 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1552 radeon_bo_unref(&rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1555 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) in r600_set_bios_scratch_engine_hung() argument
1567 static void r600_print_gpu_status_regs(struct radeon_device *rdev) in r600_print_gpu_status_regs() argument
1569 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", in r600_print_gpu_status_regs()
1571 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", in r600_print_gpu_status_regs()
1573 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", in r600_print_gpu_status_regs()
1575 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", in r600_print_gpu_status_regs()
1577 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", in r600_print_gpu_status_regs()
1579 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", in r600_print_gpu_status_regs()
1581 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", in r600_print_gpu_status_regs()
1583 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", in r600_print_gpu_status_regs()
1587 static bool r600_is_display_hung(struct radeon_device *rdev) in r600_is_display_hung() argument
1593 for (i = 0; i < rdev->num_crtc; i++) { in r600_is_display_hung()
1601 for (i = 0; i < rdev->num_crtc; i++) { in r600_is_display_hung()
1616 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) in r600_gpu_check_soft_reset() argument
1623 if (rdev->family >= CHIP_RV770) { in r600_gpu_check_soft_reset()
1673 if (r600_is_display_hung(rdev)) in r600_gpu_check_soft_reset()
1685 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in r600_gpu_soft_reset() argument
1694 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in r600_gpu_soft_reset()
1696 r600_print_gpu_status_regs(rdev); in r600_gpu_soft_reset()
1699 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1716 rv515_mc_stop(rdev, &save); in r600_gpu_soft_reset()
1717 if (r600_mc_wait_for_idle(rdev)) { in r600_gpu_soft_reset()
1718 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_soft_reset()
1722 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1758 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1776 if (!(rdev->flags & RADEON_IS_IGP)) { in r600_gpu_soft_reset()
1787 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1801 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1815 rv515_mc_resume(rdev, &save); in r600_gpu_soft_reset()
1818 r600_print_gpu_status_regs(rdev); in r600_gpu_soft_reset()
1821 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) in r600_gpu_pci_config_reset() argument
1826 dev_info(rdev->dev, "GPU pci config reset\n"); in r600_gpu_pci_config_reset()
1831 if (rdev->family >= CHIP_RV770) in r600_gpu_pci_config_reset()
1847 if (rdev->family >= CHIP_RV770) in r600_gpu_pci_config_reset()
1848 rv770_set_clk_bypass_mode(rdev); in r600_gpu_pci_config_reset()
1850 pci_clear_master(rdev->pdev); in r600_gpu_pci_config_reset()
1852 rv515_mc_stop(rdev, &save); in r600_gpu_pci_config_reset()
1853 if (r600_mc_wait_for_idle(rdev)) { in r600_gpu_pci_config_reset()
1854 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_pci_config_reset()
1865 radeon_pci_config_reset(rdev); in r600_gpu_pci_config_reset()
1875 for (i = 0; i < rdev->usec_timeout; i++) { in r600_gpu_pci_config_reset()
1882 int r600_asic_reset(struct radeon_device *rdev, bool hard) in r600_asic_reset() argument
1887 r600_gpu_pci_config_reset(rdev); in r600_asic_reset()
1891 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1894 r600_set_bios_scratch_engine_hung(rdev, true); in r600_asic_reset()
1897 r600_gpu_soft_reset(rdev, reset_mask); in r600_asic_reset()
1899 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1903 r600_gpu_pci_config_reset(rdev); in r600_asic_reset()
1905 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1908 r600_set_bios_scratch_engine_hung(rdev, false); in r600_asic_reset()
1922 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in r600_gfx_is_lockup() argument
1924 u32 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_gfx_is_lockup()
1929 radeon_ring_lockup_update(rdev, ring); in r600_gfx_is_lockup()
1932 return radeon_ring_test_lockup(rdev, ring); in r600_gfx_is_lockup()
1935 u32 r6xx_remap_render_backend(struct radeon_device *rdev, in r6xx_remap_render_backend() argument
1959 if (rdev->family <= CHIP_RV740) { in r6xx_remap_render_backend()
1990 static void r600_gpu_init(struct radeon_device *rdev) in r600_gpu_init() argument
2005 rdev->config.r600.tiling_group_size = 256; in r600_gpu_init()
2006 switch (rdev->family) { in r600_gpu_init()
2008 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
2009 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()
2010 rdev->config.r600.max_simds = 4; in r600_gpu_init()
2011 rdev->config.r600.max_backends = 4; in r600_gpu_init()
2012 rdev->config.r600.max_gprs = 256; in r600_gpu_init()
2013 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2014 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2015 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2016 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2017 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2018 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2019 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2020 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2024 rdev->config.r600.max_pipes = 2; in r600_gpu_init()
2025 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()
2026 rdev->config.r600.max_simds = 3; in r600_gpu_init()
2027 rdev->config.r600.max_backends = 1; in r600_gpu_init()
2028 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
2029 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2030 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
2031 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2032 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
2033 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2034 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2035 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2036 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2042 rdev->config.r600.max_pipes = 1; in r600_gpu_init()
2043 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()
2044 rdev->config.r600.max_simds = 2; in r600_gpu_init()
2045 rdev->config.r600.max_backends = 1; in r600_gpu_init()
2046 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
2047 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2048 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
2049 rdev->config.r600.max_hw_contexts = 4; in r600_gpu_init()
2050 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
2051 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2052 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2053 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2054 rdev->config.r600.sq_num_cf_insts = 1; in r600_gpu_init()
2057 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
2058 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()
2059 rdev->config.r600.max_simds = 4; in r600_gpu_init()
2060 rdev->config.r600.max_backends = 4; in r600_gpu_init()
2061 rdev->config.r600.max_gprs = 192; in r600_gpu_init()
2062 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2063 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2064 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2065 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2066 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2067 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2068 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2069 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2089 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()
2105 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
2106 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); in r600_gpu_init()
2121 tmp = rdev->config.r600.max_simds - in r600_gpu_init()
2123 rdev->config.r600.active_simds = tmp; in r600_gpu_init()
2127 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2131 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2135 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, in r600_gpu_init()
2138 rdev->config.r600.backend_map = tmp; in r600_gpu_init()
2140 rdev->config.r600.tile_config = tiling_config; in r600_gpu_init()
2157 if (rdev->family == CHIP_RV670) in r600_gpu_init()
2162 if ((rdev->family > CHIP_R600)) in r600_gpu_init()
2166 if (((rdev->family) == CHIP_R600) || in r600_gpu_init()
2167 ((rdev->family) == CHIP_RV630) || in r600_gpu_init()
2168 ((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2169 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2170 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2171 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2186 if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2187 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2188 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2189 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2194 } else if (((rdev->family) == CHIP_R600) || in r600_gpu_init()
2195 ((rdev->family) == CHIP_RV630)) { in r600_gpu_init()
2216 if ((rdev->family) == CHIP_R600) { in r600_gpu_init()
2230 } else if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2231 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2232 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2233 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2250 } else if (((rdev->family) == CHIP_RV630) || in r600_gpu_init()
2251 ((rdev->family) == CHIP_RV635)) { in r600_gpu_init()
2265 } else if ((rdev->family) == CHIP_RV670) { in r600_gpu_init()
2288 if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2289 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2290 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2291 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2314 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
2315 switch (rdev->family) { in r600_gpu_init()
2358 switch (rdev->family) { in r600_gpu_init()
2396 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) in r600_pciep_rreg() argument
2401 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); in r600_pciep_rreg()
2405 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); in r600_pciep_rreg()
2409 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r600_pciep_wreg() argument
2413 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); in r600_pciep_wreg()
2418 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); in r600_pciep_wreg()
2424 void r600_cp_stop(struct radeon_device *rdev) in r600_cp_stop() argument
2426 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r600_cp_stop()
2427 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r600_cp_stop()
2430 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r600_cp_stop()
2433 int r600_init_microcode(struct radeon_device *rdev) in r600_init_microcode() argument
2444 switch (rdev->family) { in r600_init_microcode()
2538 if (rdev->family >= CHIP_CEDAR) { in r600_init_microcode()
2542 } else if (rdev->family >= CHIP_RV770) { in r600_init_microcode()
2555 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in r600_init_microcode()
2558 if (rdev->pfp_fw->size != pfp_req_size) { in r600_init_microcode()
2560 rdev->pfp_fw->size, fw_name); in r600_init_microcode()
2566 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in r600_init_microcode()
2569 if (rdev->me_fw->size != me_req_size) { in r600_init_microcode()
2571 rdev->me_fw->size, fw_name); in r600_init_microcode()
2576 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in r600_init_microcode()
2579 if (rdev->rlc_fw->size != rlc_req_size) { in r600_init_microcode()
2581 rdev->rlc_fw->size, fw_name); in r600_init_microcode()
2585 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { in r600_init_microcode()
2587 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in r600_init_microcode()
2590 release_firmware(rdev->smc_fw); in r600_init_microcode()
2591 rdev->smc_fw = NULL; in r600_init_microcode()
2593 } else if (rdev->smc_fw->size != smc_req_size) { in r600_init_microcode()
2595 rdev->smc_fw->size, fw_name); in r600_init_microcode()
2605 release_firmware(rdev->pfp_fw); in r600_init_microcode()
2606 rdev->pfp_fw = NULL; in r600_init_microcode()
2607 release_firmware(rdev->me_fw); in r600_init_microcode()
2608 rdev->me_fw = NULL; in r600_init_microcode()
2609 release_firmware(rdev->rlc_fw); in r600_init_microcode()
2610 rdev->rlc_fw = NULL; in r600_init_microcode()
2611 release_firmware(rdev->smc_fw); in r600_init_microcode()
2612 rdev->smc_fw = NULL; in r600_init_microcode()
2617 u32 r600_gfx_get_rptr(struct radeon_device *rdev, in r600_gfx_get_rptr() argument
2622 if (rdev->wb.enabled) in r600_gfx_get_rptr()
2623 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_gfx_get_rptr()
2630 u32 r600_gfx_get_wptr(struct radeon_device *rdev, in r600_gfx_get_wptr() argument
2636 void r600_gfx_set_wptr(struct radeon_device *rdev, in r600_gfx_set_wptr() argument
2643 static int r600_cp_load_microcode(struct radeon_device *rdev) in r600_cp_load_microcode() argument
2648 if (!rdev->me_fw || !rdev->pfp_fw) in r600_cp_load_microcode()
2651 r600_cp_stop(rdev); in r600_cp_load_microcode()
2667 fw_data = (const __be32 *)rdev->me_fw->data; in r600_cp_load_microcode()
2673 fw_data = (const __be32 *)rdev->pfp_fw->data; in r600_cp_load_microcode()
2685 int r600_cp_start(struct radeon_device *rdev) in r600_cp_start() argument
2687 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_start()
2691 r = radeon_ring_lock(rdev, ring, 7); in r600_cp_start()
2698 if (rdev->family >= CHIP_RV770) { in r600_cp_start()
2700 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2703 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2708 radeon_ring_unlock_commit(rdev, ring, false); in r600_cp_start()
2715 int r600_cp_resume(struct radeon_device *rdev) in r600_cp_resume() argument
2717 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_resume()
2748 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_cp_resume()
2749 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2750 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2752 if (rdev->wb.enabled) in r600_cp_resume()
2765 r600_cp_start(rdev); in r600_cp_resume()
2767 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in r600_cp_resume()
2773 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r600_cp_resume()
2774 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r600_cp_resume()
2779 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) in r600_ring_init() argument
2790 if (radeon_ring_supports_scratch_reg(rdev, ring)) { in r600_ring_init()
2791 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); in r600_ring_init()
2799 void r600_cp_fini(struct radeon_device *rdev) in r600_cp_fini() argument
2801 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_fini()
2802 r600_cp_stop(rdev); in r600_cp_fini()
2803 radeon_ring_fini(rdev, ring); in r600_cp_fini()
2804 radeon_scratch_free(rdev, ring->rptr_save_reg); in r600_cp_fini()
2810 void r600_scratch_init(struct radeon_device *rdev) in r600_scratch_init() argument
2814 rdev->scratch.num_reg = 7; in r600_scratch_init()
2815 rdev->scratch.reg_base = SCRATCH_REG0; in r600_scratch_init()
2816 for (i = 0; i < rdev->scratch.num_reg; i++) { in r600_scratch_init()
2817 rdev->scratch.free[i] = true; in r600_scratch_init()
2818 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in r600_scratch_init()
2822 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) in r600_ring_test() argument
2829 r = radeon_scratch_get(rdev, &scratch); in r600_ring_test()
2835 r = radeon_ring_lock(rdev, ring, 3); in r600_ring_test()
2838 radeon_scratch_free(rdev, scratch); in r600_ring_test()
2844 radeon_ring_unlock_commit(rdev, ring, false); in r600_ring_test()
2845 for (i = 0; i < rdev->usec_timeout; i++) { in r600_ring_test()
2851 if (i < rdev->usec_timeout) { in r600_ring_test()
2858 radeon_scratch_free(rdev, scratch); in r600_ring_test()
2866 void r600_fence_ring_emit(struct radeon_device *rdev, in r600_fence_ring_emit() argument
2869 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r600_fence_ring_emit()
2873 if (rdev->family >= CHIP_RV770) in r600_fence_ring_emit()
2876 if (rdev->wb.use_event) { in r600_fence_ring_emit()
2877 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_fence_ring_emit()
2906 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
2925 bool r600_semaphore_ring_emit(struct radeon_device *rdev, in r600_semaphore_ring_emit() argument
2933 if (rdev->family < CHIP_CAYMAN) in r600_semaphore_ring_emit()
2941 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { in r600_semaphore_ring_emit()
2963 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, in r600_copy_cpdma() argument
2970 int ring_index = rdev->asic->copy.blit_ring_index; in r600_copy_cpdma()
2971 struct radeon_ring *ring = &rdev->ring[ring_index]; in r600_copy_cpdma()
2980 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); in r600_copy_cpdma()
2983 radeon_sync_free(rdev, &sync, NULL); in r600_copy_cpdma()
2987 radeon_sync_resv(rdev, &sync, resv, false); in r600_copy_cpdma()
2988 radeon_sync_rings(rdev, &sync, ring->idx); in r600_copy_cpdma()
3014 r = radeon_fence_emit(rdev, &fence, ring->idx); in r600_copy_cpdma()
3016 radeon_ring_unlock_undo(rdev, ring); in r600_copy_cpdma()
3017 radeon_sync_free(rdev, &sync, NULL); in r600_copy_cpdma()
3021 radeon_ring_unlock_commit(rdev, ring, false); in r600_copy_cpdma()
3022 radeon_sync_free(rdev, &sync, fence); in r600_copy_cpdma()
3027 int r600_set_surface_reg(struct radeon_device *rdev, int reg, in r600_set_surface_reg() argument
3035 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) in r600_clear_surface_reg() argument
3040 static void r600_uvd_init(struct radeon_device *rdev) in r600_uvd_init() argument
3044 if (!rdev->has_uvd) in r600_uvd_init()
3047 r = radeon_uvd_init(rdev); in r600_uvd_init()
3049 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in r600_uvd_init()
3056 rdev->has_uvd = 0; in r600_uvd_init()
3059 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in r600_uvd_init()
3060 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in r600_uvd_init()
3063 static void r600_uvd_start(struct radeon_device *rdev) in r600_uvd_start() argument
3067 if (!rdev->has_uvd) in r600_uvd_start()
3070 r = uvd_v1_0_resume(rdev); in r600_uvd_start()
3072 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in r600_uvd_start()
3075 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); in r600_uvd_start()
3077 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in r600_uvd_start()
3083 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in r600_uvd_start()
3086 static void r600_uvd_resume(struct radeon_device *rdev) in r600_uvd_resume() argument
3091 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in r600_uvd_resume()
3094 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in r600_uvd_resume()
3095 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in r600_uvd_resume()
3097 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in r600_uvd_resume()
3100 r = uvd_v1_0_init(rdev); in r600_uvd_resume()
3102 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in r600_uvd_resume()
3107 static int r600_startup(struct radeon_device *rdev) in r600_startup() argument
3113 r600_pcie_gen2_enable(rdev); in r600_startup()
3116 r = r600_vram_scratch_init(rdev); in r600_startup()
3120 r600_mc_program(rdev); in r600_startup()
3122 if (rdev->flags & RADEON_IS_AGP) { in r600_startup()
3123 r600_agp_enable(rdev); in r600_startup()
3125 r = r600_pcie_gart_enable(rdev); in r600_startup()
3129 r600_gpu_init(rdev); in r600_startup()
3132 r = radeon_wb_init(rdev); in r600_startup()
3136 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r600_startup()
3138 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r600_startup()
3142 r600_uvd_start(rdev); in r600_startup()
3145 if (!rdev->irq.installed) { in r600_startup()
3146 r = radeon_irq_kms_init(rdev); in r600_startup()
3151 r = r600_irq_init(rdev); in r600_startup()
3154 radeon_irq_kms_fini(rdev); in r600_startup()
3157 r600_irq_set(rdev); in r600_startup()
3159 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_startup()
3160 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in r600_startup()
3165 r = r600_cp_load_microcode(rdev); in r600_startup()
3168 r = r600_cp_resume(rdev); in r600_startup()
3172 r600_uvd_resume(rdev); in r600_startup()
3174 r = radeon_ib_pool_init(rdev); in r600_startup()
3176 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r600_startup()
3180 r = radeon_audio_init(rdev); in r600_startup()
3189 void r600_vga_set_state(struct radeon_device *rdev, bool state) in r600_vga_set_state() argument
3203 int r600_resume(struct radeon_device *rdev) in r600_resume() argument
3212 atom_asic_init(rdev->mode_info.atom_context); in r600_resume()
3214 if (rdev->pm.pm_method == PM_METHOD_DPM) in r600_resume()
3215 radeon_pm_resume(rdev); in r600_resume()
3217 rdev->accel_working = true; in r600_resume()
3218 r = r600_startup(rdev); in r600_resume()
3221 rdev->accel_working = false; in r600_resume()
3228 int r600_suspend(struct radeon_device *rdev) in r600_suspend() argument
3230 radeon_pm_suspend(rdev); in r600_suspend()
3231 radeon_audio_fini(rdev); in r600_suspend()
3232 r600_cp_stop(rdev); in r600_suspend()
3233 if (rdev->has_uvd) { in r600_suspend()
3234 uvd_v1_0_fini(rdev); in r600_suspend()
3235 radeon_uvd_suspend(rdev); in r600_suspend()
3237 r600_irq_suspend(rdev); in r600_suspend()
3238 radeon_wb_disable(rdev); in r600_suspend()
3239 r600_pcie_gart_disable(rdev); in r600_suspend()
3250 int r600_init(struct radeon_device *rdev) in r600_init() argument
3254 if (r600_debugfs_mc_info_init(rdev)) { in r600_init()
3258 if (!radeon_get_bios(rdev)) { in r600_init()
3259 if (ASIC_IS_AVIVO(rdev)) in r600_init()
3263 if (!rdev->is_atom_bios) { in r600_init()
3264 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); in r600_init()
3267 r = radeon_atombios_init(rdev); in r600_init()
3271 if (!radeon_card_posted(rdev)) { in r600_init()
3272 if (!rdev->bios) { in r600_init()
3273 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in r600_init()
3277 atom_asic_init(rdev->mode_info.atom_context); in r600_init()
3280 r600_scratch_init(rdev); in r600_init()
3282 radeon_surface_init(rdev); in r600_init()
3284 radeon_get_clock_info(rdev->ddev); in r600_init()
3286 r = radeon_fence_driver_init(rdev); in r600_init()
3289 if (rdev->flags & RADEON_IS_AGP) { in r600_init()
3290 r = radeon_agp_init(rdev); in r600_init()
3292 radeon_agp_disable(rdev); in r600_init()
3294 r = r600_mc_init(rdev); in r600_init()
3298 r = radeon_bo_init(rdev); in r600_init()
3302 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in r600_init()
3303 r = r600_init_microcode(rdev); in r600_init()
3311 radeon_pm_init(rdev); in r600_init()
3313 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in r600_init()
3314 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in r600_init()
3316 r600_uvd_init(rdev); in r600_init()
3318 rdev->ih.ring_obj = NULL; in r600_init()
3319 r600_ih_ring_init(rdev, 64 * 1024); in r600_init()
3321 r = r600_pcie_gart_init(rdev); in r600_init()
3325 rdev->accel_working = true; in r600_init()
3326 r = r600_startup(rdev); in r600_init()
3328 dev_err(rdev->dev, "disabling GPU acceleration\n"); in r600_init()
3329 r600_cp_fini(rdev); in r600_init()
3330 r600_irq_fini(rdev); in r600_init()
3331 radeon_wb_fini(rdev); in r600_init()
3332 radeon_ib_pool_fini(rdev); in r600_init()
3333 radeon_irq_kms_fini(rdev); in r600_init()
3334 r600_pcie_gart_fini(rdev); in r600_init()
3335 rdev->accel_working = false; in r600_init()
3341 void r600_fini(struct radeon_device *rdev) in r600_fini() argument
3343 radeon_pm_fini(rdev); in r600_fini()
3344 radeon_audio_fini(rdev); in r600_fini()
3345 r600_cp_fini(rdev); in r600_fini()
3346 r600_irq_fini(rdev); in r600_fini()
3347 if (rdev->has_uvd) { in r600_fini()
3348 uvd_v1_0_fini(rdev); in r600_fini()
3349 radeon_uvd_fini(rdev); in r600_fini()
3351 radeon_wb_fini(rdev); in r600_fini()
3352 radeon_ib_pool_fini(rdev); in r600_fini()
3353 radeon_irq_kms_fini(rdev); in r600_fini()
3354 r600_pcie_gart_fini(rdev); in r600_fini()
3355 r600_vram_scratch_fini(rdev); in r600_fini()
3356 radeon_agp_fini(rdev); in r600_fini()
3357 radeon_gem_fini(rdev); in r600_fini()
3358 radeon_fence_driver_fini(rdev); in r600_fini()
3359 radeon_bo_fini(rdev); in r600_fini()
3360 radeon_atombios_fini(rdev); in r600_fini()
3361 kfree(rdev->bios); in r600_fini()
3362 rdev->bios = NULL; in r600_fini()
3369 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in r600_ring_ib_execute() argument
3371 struct radeon_ring *ring = &rdev->ring[ib->ring]; in r600_ring_ib_execute()
3380 } else if (rdev->wb.enabled) { in r600_ring_ib_execute()
3399 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) in r600_ib_test() argument
3407 r = radeon_scratch_get(rdev, &scratch); in r600_ib_test()
3413 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); in r600_ib_test()
3422 r = radeon_ib_schedule(rdev, &ib, NULL, false); in r600_ib_test()
3438 for (i = 0; i < rdev->usec_timeout; i++) { in r600_ib_test()
3444 if (i < rdev->usec_timeout) { in r600_ib_test()
3452 radeon_ib_free(rdev, &ib); in r600_ib_test()
3454 radeon_scratch_free(rdev, scratch); in r600_ib_test()
3469 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) in r600_ih_ring_init() argument
3476 rdev->ih.ring_size = ring_size; in r600_ih_ring_init()
3477 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; in r600_ih_ring_init()
3478 rdev->ih.rptr = 0; in r600_ih_ring_init()
3481 int r600_ih_ring_alloc(struct radeon_device *rdev) in r600_ih_ring_alloc() argument
3486 if (rdev->ih.ring_obj == NULL) { in r600_ih_ring_alloc()
3487 r = radeon_bo_create(rdev, rdev->ih.ring_size, in r600_ih_ring_alloc()
3490 NULL, NULL, &rdev->ih.ring_obj); in r600_ih_ring_alloc()
3495 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_alloc()
3498 r = radeon_bo_pin(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3500 &rdev->ih.gpu_addr); in r600_ih_ring_alloc()
3502 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3506 r = radeon_bo_kmap(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3507 (void **)&rdev->ih.ring); in r600_ih_ring_alloc()
3508 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3517 void r600_ih_ring_fini(struct radeon_device *rdev) in r600_ih_ring_fini() argument
3520 if (rdev->ih.ring_obj) { in r600_ih_ring_fini()
3521 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_fini()
3523 radeon_bo_kunmap(rdev->ih.ring_obj); in r600_ih_ring_fini()
3524 radeon_bo_unpin(rdev->ih.ring_obj); in r600_ih_ring_fini()
3525 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_fini()
3527 radeon_bo_unref(&rdev->ih.ring_obj); in r600_ih_ring_fini()
3528 rdev->ih.ring = NULL; in r600_ih_ring_fini()
3529 rdev->ih.ring_obj = NULL; in r600_ih_ring_fini()
3533 void r600_rlc_stop(struct radeon_device *rdev) in r600_rlc_stop() argument
3536 if ((rdev->family >= CHIP_RV770) && in r600_rlc_stop()
3537 (rdev->family <= CHIP_RV740)) { in r600_rlc_stop()
3549 static void r600_rlc_start(struct radeon_device *rdev) in r600_rlc_start() argument
3554 static int r600_rlc_resume(struct radeon_device *rdev) in r600_rlc_resume() argument
3559 if (!rdev->rlc_fw) in r600_rlc_resume()
3562 r600_rlc_stop(rdev); in r600_rlc_resume()
3574 fw_data = (const __be32 *)rdev->rlc_fw->data; in r600_rlc_resume()
3575 if (rdev->family >= CHIP_RV770) { in r600_rlc_resume()
3588 r600_rlc_start(rdev); in r600_rlc_resume()
3593 static void r600_enable_interrupts(struct radeon_device *rdev) in r600_enable_interrupts() argument
3602 rdev->ih.enabled = true; in r600_enable_interrupts()
3605 void r600_disable_interrupts(struct radeon_device *rdev) in r600_disable_interrupts() argument
3617 rdev->ih.enabled = false; in r600_disable_interrupts()
3618 rdev->ih.rptr = 0; in r600_disable_interrupts()
3621 static void r600_disable_interrupt_state(struct radeon_device *rdev) in r600_disable_interrupt_state() argument
3632 if (ASIC_IS_DCE3(rdev)) { in r600_disable_interrupt_state()
3643 if (ASIC_IS_DCE32(rdev)) { in r600_disable_interrupt_state()
3674 int r600_irq_init(struct radeon_device *rdev) in r600_irq_init() argument
3681 ret = r600_ih_ring_alloc(rdev); in r600_irq_init()
3686 r600_disable_interrupts(rdev); in r600_irq_init()
3689 if (rdev->family >= CHIP_CEDAR) in r600_irq_init()
3690 ret = evergreen_rlc_resume(rdev); in r600_irq_init()
3692 ret = r600_rlc_resume(rdev); in r600_irq_init()
3694 r600_ih_ring_fini(rdev); in r600_irq_init()
3700 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); in r600_irq_init()
3710 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3711 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in r600_irq_init()
3717 if (rdev->wb.enabled) in r600_irq_init()
3721 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in r600_irq_init()
3722 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in r600_irq_init()
3733 if (rdev->msi_enabled) in r600_irq_init()
3738 if (rdev->family >= CHIP_CEDAR) in r600_irq_init()
3739 evergreen_disable_interrupt_state(rdev); in r600_irq_init()
3741 r600_disable_interrupt_state(rdev); in r600_irq_init()
3744 pci_set_master(rdev->pdev); in r600_irq_init()
3747 r600_enable_interrupts(rdev); in r600_irq_init()
3752 void r600_irq_suspend(struct radeon_device *rdev) in r600_irq_suspend() argument
3754 r600_irq_disable(rdev); in r600_irq_suspend()
3755 r600_rlc_stop(rdev); in r600_irq_suspend()
3758 void r600_irq_fini(struct radeon_device *rdev) in r600_irq_fini() argument
3760 r600_irq_suspend(rdev); in r600_irq_fini()
3761 r600_ih_ring_fini(rdev); in r600_irq_fini()
3764 int r600_irq_set(struct radeon_device *rdev) in r600_irq_set() argument
3774 if (!rdev->irq.installed) { in r600_irq_set()
3779 if (!rdev->ih.enabled) { in r600_irq_set()
3780 r600_disable_interrupts(rdev); in r600_irq_set()
3782 r600_disable_interrupt_state(rdev); in r600_irq_set()
3786 if (ASIC_IS_DCE3(rdev)) { in r600_irq_set()
3791 if (ASIC_IS_DCE32(rdev)) { in r600_irq_set()
3810 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { in r600_irq_set()
3813 } else if (rdev->family >= CHIP_RV770) { in r600_irq_set()
3817 if (rdev->irq.dpm_thermal) { in r600_irq_set()
3822 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in r600_irq_set()
3828 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { in r600_irq_set()
3833 if (rdev->irq.crtc_vblank_int[0] || in r600_irq_set()
3834 atomic_read(&rdev->irq.pflip[0])) { in r600_irq_set()
3838 if (rdev->irq.crtc_vblank_int[1] || in r600_irq_set()
3839 atomic_read(&rdev->irq.pflip[1])) { in r600_irq_set()
3843 if (rdev->irq.hpd[0]) { in r600_irq_set()
3847 if (rdev->irq.hpd[1]) { in r600_irq_set()
3851 if (rdev->irq.hpd[2]) { in r600_irq_set()
3855 if (rdev->irq.hpd[3]) { in r600_irq_set()
3859 if (rdev->irq.hpd[4]) { in r600_irq_set()
3863 if (rdev->irq.hpd[5]) { in r600_irq_set()
3867 if (rdev->irq.afmt[0]) { in r600_irq_set()
3871 if (rdev->irq.afmt[1]) { in r600_irq_set()
3882 if (ASIC_IS_DCE3(rdev)) { in r600_irq_set()
3887 if (ASIC_IS_DCE32(rdev)) { in r600_irq_set()
3903 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { in r600_irq_set()
3905 } else if (rdev->family >= CHIP_RV770) { in r600_irq_set()
3915 static void r600_irq_ack(struct radeon_device *rdev) in r600_irq_ack() argument
3919 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3920 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3921 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3922 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3923 if (ASIC_IS_DCE32(rdev)) { in r600_irq_ack()
3924 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3925 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3927 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3928 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); in r600_irq_ack()
3931 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3932 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3933 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; in r600_irq_ack()
3934 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3935 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); in r600_irq_ack()
3937 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3938 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3940 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3942 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3944 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3946 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3948 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3950 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3952 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3953 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3963 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
3964 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3974 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_ack()
3975 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3985 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_ack()
3990 if (ASIC_IS_DCE32(rdev)) { in r600_irq_ack()
3991 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_ack()
3996 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_ack()
4001 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4006 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4012 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4017 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4018 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
4031 void r600_irq_disable(struct radeon_device *rdev) in r600_irq_disable() argument
4033 r600_disable_interrupts(rdev); in r600_irq_disable()
4036 r600_irq_ack(rdev); in r600_irq_disable()
4037 r600_disable_interrupt_state(rdev); in r600_irq_disable()
4040 static u32 r600_get_ih_wptr(struct radeon_device *rdev) in r600_get_ih_wptr() argument
4044 if (rdev->wb.enabled) in r600_get_ih_wptr()
4045 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in r600_get_ih_wptr()
4055 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in r600_get_ih_wptr()
4056 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in r600_get_ih_wptr()
4057 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in r600_get_ih_wptr()
4062 return (wptr & rdev->ih.ptr_mask); in r600_get_ih_wptr()
4095 int r600_irq_process(struct radeon_device *rdev) in r600_irq_process() argument
4105 if (!rdev->ih.enabled || rdev->shutdown) in r600_irq_process()
4109 if (!rdev->msi_enabled) in r600_irq_process()
4112 wptr = r600_get_ih_wptr(rdev); in r600_irq_process()
4116 if (atomic_xchg(&rdev->ih.lock, 1)) in r600_irq_process()
4119 rptr = rdev->ih.rptr; in r600_irq_process()
4126 r600_irq_ack(rdev); in r600_irq_process()
4131 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in r600_irq_process()
4132 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in r600_irq_process()
4138 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) in r600_irq_process()
4141 if (rdev->irq.crtc_vblank_int[0]) { in r600_irq_process()
4142 drm_handle_vblank(rdev->ddev, 0); in r600_irq_process()
4143 rdev->pm.vblank_sync = true; in r600_irq_process()
4144 wake_up(&rdev->irq.vblank_queue); in r600_irq_process()
4146 if (atomic_read(&rdev->irq.pflip[0])) in r600_irq_process()
4147 radeon_crtc_handle_vblank(rdev, 0); in r600_irq_process()
4148 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
4153 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) in r600_irq_process()
4156 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; in r600_irq_process()
4168 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) in r600_irq_process()
4171 if (rdev->irq.crtc_vblank_int[1]) { in r600_irq_process()
4172 drm_handle_vblank(rdev->ddev, 1); in r600_irq_process()
4173 rdev->pm.vblank_sync = true; in r600_irq_process()
4174 wake_up(&rdev->irq.vblank_queue); in r600_irq_process()
4176 if (atomic_read(&rdev->irq.pflip[1])) in r600_irq_process()
4177 radeon_crtc_handle_vblank(rdev, 1); in r600_irq_process()
4178 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; in r600_irq_process()
4183 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) in r600_irq_process()
4186 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; in r600_irq_process()
4198 radeon_crtc_handle_flip(rdev, 0); in r600_irq_process()
4203 radeon_crtc_handle_flip(rdev, 1); in r600_irq_process()
4208 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) in r600_irq_process()
4211 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; in r600_irq_process()
4216 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) in r600_irq_process()
4219 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; in r600_irq_process()
4224 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) in r600_irq_process()
4227 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; in r600_irq_process()
4232 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) in r600_irq_process()
4235 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; in r600_irq_process()
4240 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) in r600_irq_process()
4243 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; in r600_irq_process()
4248 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) in r600_irq_process()
4251 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; in r600_irq_process()
4264 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4267 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4273 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4276 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4288 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); in r600_irq_process()
4294 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in r600_irq_process()
4298 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in r600_irq_process()
4302 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); in r600_irq_process()
4306 rdev->pm.dpm.thermal.high_to_low = false; in r600_irq_process()
4311 rdev->pm.dpm.thermal.high_to_low = true; in r600_irq_process()
4324 rptr &= rdev->ih.ptr_mask; in r600_irq_process()
4328 schedule_delayed_work(&rdev->hotplug_work, 0); in r600_irq_process()
4330 schedule_work(&rdev->audio_work); in r600_irq_process()
4331 if (queue_thermal && rdev->pm.dpm_enabled) in r600_irq_process()
4332 schedule_work(&rdev->pm.dpm.thermal.work); in r600_irq_process()
4333 rdev->ih.rptr = rptr; in r600_irq_process()
4334 atomic_set(&rdev->ih.lock, 0); in r600_irq_process()
4337 wptr = r600_get_ih_wptr(rdev); in r600_irq_process()
4353 struct radeon_device *rdev = dev->dev_private; in r600_debugfs_mc_info() local
4355 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); in r600_debugfs_mc_info()
4356 DREG32_SYS(m, rdev, VM_L2_STATUS); in r600_debugfs_mc_info()
4365 int r600_debugfs_mc_info_init(struct radeon_device *rdev) in r600_debugfs_mc_info_init() argument
4368 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); in r600_debugfs_mc_info_init()
4383 void r600_mmio_hdp_flush(struct radeon_device *rdev) in r600_mmio_hdp_flush() argument
4390 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && in r600_mmio_hdp_flush()
4391 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { in r600_mmio_hdp_flush()
4392 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; in r600_mmio_hdp_flush()
4401 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) in r600_set_pcie_lanes() argument
4405 if (rdev->flags & RADEON_IS_IGP) in r600_set_pcie_lanes()
4408 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_set_pcie_lanes()
4412 if (ASIC_IS_X2(rdev)) in r600_set_pcie_lanes()
4415 radeon_gui_idle(rdev); in r600_set_pcie_lanes()
4454 int r600_get_pcie_lanes(struct radeon_device *rdev) in r600_get_pcie_lanes() argument
4458 if (rdev->flags & RADEON_IS_IGP) in r600_get_pcie_lanes()
4461 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_get_pcie_lanes()
4465 if (ASIC_IS_X2(rdev)) in r600_get_pcie_lanes()
4468 radeon_gui_idle(rdev); in r600_get_pcie_lanes()
4491 static void r600_pcie_gen2_enable(struct radeon_device *rdev) in r600_pcie_gen2_enable() argument
4499 if (rdev->flags & RADEON_IS_IGP) in r600_pcie_gen2_enable()
4502 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_pcie_gen2_enable()
4506 if (ASIC_IS_X2(rdev)) in r600_pcie_gen2_enable()
4510 if (rdev->family <= CHIP_R600) in r600_pcie_gen2_enable()
4513 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && in r600_pcie_gen2_enable()
4514 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) in r600_pcie_gen2_enable()
4526 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4527 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4528 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4551 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4552 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4553 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4578 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4579 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4580 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4613 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) in r600_get_gpu_clock_counter() argument
4617 mutex_lock(&rdev->gpu_clock_mutex); in r600_get_gpu_clock_counter()
4621 mutex_unlock(&rdev->gpu_clock_mutex); in r600_get_gpu_clock_counter()