Lines Matching refs:reset_mask
1618 u32 reset_mask = 0; in r600_gpu_check_soft_reset() local
1629 reset_mask |= RADEON_RESET_GFX; in r600_gpu_check_soft_reset()
1636 reset_mask |= RADEON_RESET_GFX; in r600_gpu_check_soft_reset()
1641 reset_mask |= RADEON_RESET_CP; in r600_gpu_check_soft_reset()
1644 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in r600_gpu_check_soft_reset()
1649 reset_mask |= RADEON_RESET_DMA; in r600_gpu_check_soft_reset()
1654 reset_mask |= RADEON_RESET_RLC; in r600_gpu_check_soft_reset()
1657 reset_mask |= RADEON_RESET_IH; in r600_gpu_check_soft_reset()
1660 reset_mask |= RADEON_RESET_SEM; in r600_gpu_check_soft_reset()
1663 reset_mask |= RADEON_RESET_GRBM; in r600_gpu_check_soft_reset()
1666 reset_mask |= RADEON_RESET_VMC; in r600_gpu_check_soft_reset()
1671 reset_mask |= RADEON_RESET_MC; in r600_gpu_check_soft_reset()
1674 reset_mask |= RADEON_RESET_DISPLAY; in r600_gpu_check_soft_reset()
1677 if (reset_mask & RADEON_RESET_MC) { in r600_gpu_check_soft_reset()
1678 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); in r600_gpu_check_soft_reset()
1679 reset_mask &= ~RADEON_RESET_MC; in r600_gpu_check_soft_reset()
1682 return reset_mask; in r600_gpu_check_soft_reset()
1685 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in r600_gpu_soft_reset() argument
1691 if (reset_mask == 0) in r600_gpu_soft_reset()
1694 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in r600_gpu_soft_reset()
1707 if (reset_mask & RADEON_RESET_DMA) { in r600_gpu_soft_reset()
1721 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { in r600_gpu_soft_reset()
1750 if (reset_mask & RADEON_RESET_CP) { in r600_gpu_soft_reset()
1757 if (reset_mask & RADEON_RESET_DMA) { in r600_gpu_soft_reset()
1764 if (reset_mask & RADEON_RESET_RLC) in r600_gpu_soft_reset()
1767 if (reset_mask & RADEON_RESET_SEM) in r600_gpu_soft_reset()
1770 if (reset_mask & RADEON_RESET_IH) in r600_gpu_soft_reset()
1773 if (reset_mask & RADEON_RESET_GRBM) in r600_gpu_soft_reset()
1777 if (reset_mask & RADEON_RESET_MC) in r600_gpu_soft_reset()
1781 if (reset_mask & RADEON_RESET_VMC) in r600_gpu_soft_reset()
1884 u32 reset_mask; in r600_asic_reset() local
1891 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1893 if (reset_mask) in r600_asic_reset()
1897 r600_gpu_soft_reset(rdev, reset_mask); in r600_asic_reset()
1899 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1902 if (reset_mask && radeon_hard_reset) in r600_asic_reset()
1905 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1907 if (!reset_mask) in r600_asic_reset()
1924 u32 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_gfx_is_lockup() local
1926 if (!(reset_mask & (RADEON_RESET_GFX | in r600_gfx_is_lockup()