Lines Matching refs:rdev
52 static void rs600_gpu_init(struct radeon_device *rdev);
53 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
61 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) in avivo_is_in_vblank() argument
69 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) in avivo_is_counter_moving() argument
90 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) in avivo_wait_for_vblank() argument
94 if (crtc >= rdev->num_crtc) in avivo_wait_for_vblank()
103 while (avivo_is_in_vblank(rdev, crtc)) { in avivo_wait_for_vblank()
105 if (!avivo_is_counter_moving(rdev, crtc)) in avivo_wait_for_vblank()
110 while (!avivo_is_in_vblank(rdev, crtc)) { in avivo_wait_for_vblank()
112 if (!avivo_is_counter_moving(rdev, crtc)) in avivo_wait_for_vblank()
118 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) in rs600_page_flip() argument
120 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
137 for (i = 0; i < rdev->usec_timeout; i++) { in rs600_page_flip()
149 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id) in rs600_page_flip_pending() argument
151 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending()
161 struct radeon_device *rdev = dev->dev_private; in avivo_program_fmt() local
222 void rs600_pm_misc(struct radeon_device *rdev) in rs600_pm_misc() argument
224 int requested_index = rdev->pm.requested_power_state_index; in rs600_pm_misc()
225 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; in rs600_pm_misc()
251 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); in rs600_pm_misc()
305 if ((rdev->flags & RADEON_IS_PCIE) && in rs600_pm_misc()
306 !(rdev->flags & RADEON_IS_IGP) && in rs600_pm_misc()
307 rdev->asic->pm.set_pcie_lanes && in rs600_pm_misc()
309 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { in rs600_pm_misc()
310 radeon_set_pcie_lanes(rdev, in rs600_pm_misc()
316 void rs600_pm_prepare(struct radeon_device *rdev) in rs600_pm_prepare() argument
318 struct drm_device *ddev = rdev->ddev; in rs600_pm_prepare()
334 void rs600_pm_finish(struct radeon_device *rdev) in rs600_pm_finish() argument
336 struct drm_device *ddev = rdev->ddev; in rs600_pm_finish()
353 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) in rs600_hpd_sense() argument
375 void rs600_hpd_set_polarity(struct radeon_device *rdev, in rs600_hpd_set_polarity() argument
379 bool connected = rs600_hpd_sense(rdev, hpd); in rs600_hpd_set_polarity()
403 void rs600_hpd_init(struct radeon_device *rdev) in rs600_hpd_init() argument
405 struct drm_device *dev = rdev->ddev; in rs600_hpd_init()
425 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in rs600_hpd_init()
427 radeon_irq_kms_enable_hpd(rdev, enable); in rs600_hpd_init()
430 void rs600_hpd_fini(struct radeon_device *rdev) in rs600_hpd_fini() argument
432 struct drm_device *dev = rdev->ddev; in rs600_hpd_fini()
453 radeon_irq_kms_disable_hpd(rdev, disable); in rs600_hpd_fini()
456 int rs600_asic_reset(struct radeon_device *rdev, bool hard) in rs600_asic_reset() argument
467 rv515_mc_stop(rdev, &save); in rs600_asic_reset()
469 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
477 pci_save_state(rdev->pdev); in rs600_asic_reset()
479 pci_clear_master(rdev->pdev); in rs600_asic_reset()
489 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
497 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
505 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
507 pci_restore_state(rdev->pdev); in rs600_asic_reset()
510 dev_err(rdev->dev, "failed to reset GPU\n"); in rs600_asic_reset()
513 dev_info(rdev->dev, "GPU reset succeed\n"); in rs600_asic_reset()
514 rv515_mc_resume(rdev, &save); in rs600_asic_reset()
521 void rs600_gart_tlb_flush(struct radeon_device *rdev) in rs600_gart_tlb_flush() argument
539 static int rs600_gart_init(struct radeon_device *rdev) in rs600_gart_init() argument
543 if (rdev->gart.robj) { in rs600_gart_init()
548 r = radeon_gart_init(rdev); in rs600_gart_init()
552 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
553 return radeon_gart_table_vram_alloc(rdev); in rs600_gart_init()
556 static int rs600_gart_enable(struct radeon_device *rdev) in rs600_gart_enable() argument
561 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
562 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rs600_gart_enable()
565 r = radeon_gart_table_vram_pin(rdev); in rs600_gart_enable()
598 rdev->gart.table_addr); in rs600_gart_enable()
599 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); in rs600_gart_enable()
600 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); in rs600_gart_enable()
604 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); in rs600_gart_enable()
605 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); in rs600_gart_enable()
612 rs600_gart_tlb_flush(rdev); in rs600_gart_enable()
614 (unsigned)(rdev->mc.gtt_size >> 20), in rs600_gart_enable()
615 (unsigned long long)rdev->gart.table_addr); in rs600_gart_enable()
616 rdev->gart.ready = true; in rs600_gart_enable()
620 static void rs600_gart_disable(struct radeon_device *rdev) in rs600_gart_disable() argument
628 radeon_gart_table_vram_unpin(rdev); in rs600_gart_disable()
631 static void rs600_gart_fini(struct radeon_device *rdev) in rs600_gart_fini() argument
633 radeon_gart_fini(rdev); in rs600_gart_fini()
634 rs600_gart_disable(rdev); in rs600_gart_fini()
635 radeon_gart_table_vram_free(rdev); in rs600_gart_fini()
653 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, in rs600_gart_set_page() argument
656 void __iomem *ptr = (void *)rdev->gart.ptr; in rs600_gart_set_page()
660 int rs600_irq_set(struct radeon_device *rdev) in rs600_irq_set() argument
669 if (ASIC_IS_DCE2(rdev)) in rs600_irq_set()
675 if (!rdev->irq.installed) { in rs600_irq_set()
680 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in rs600_irq_set()
683 if (rdev->irq.crtc_vblank_int[0] || in rs600_irq_set()
684 atomic_read(&rdev->irq.pflip[0])) { in rs600_irq_set()
687 if (rdev->irq.crtc_vblank_int[1] || in rs600_irq_set()
688 atomic_read(&rdev->irq.pflip[1])) { in rs600_irq_set()
691 if (rdev->irq.hpd[0]) { in rs600_irq_set()
694 if (rdev->irq.hpd[1]) { in rs600_irq_set()
697 if (rdev->irq.afmt[0]) { in rs600_irq_set()
704 if (ASIC_IS_DCE2(rdev)) in rs600_irq_set()
713 static inline u32 rs600_irq_ack(struct radeon_device *rdev) in rs600_irq_ack() argument
720 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); in rs600_irq_ack()
721 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
725 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
729 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
734 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
740 rdev->irq.stat_regs.r500.disp_int = 0; in rs600_irq_ack()
743 if (ASIC_IS_DCE2(rdev)) { in rs600_irq_ack()
744 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & in rs600_irq_ack()
746 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { in rs600_irq_ack()
752 rdev->irq.stat_regs.r500.hdmi0_status = 0; in rs600_irq_ack()
760 void rs600_irq_disable(struct radeon_device *rdev) in rs600_irq_disable() argument
769 rs600_irq_ack(rdev); in rs600_irq_disable()
772 int rs600_irq_process(struct radeon_device *rdev) in rs600_irq_process() argument
778 status = rs600_irq_ack(rdev); in rs600_irq_process()
780 !rdev->irq.stat_regs.r500.disp_int && in rs600_irq_process()
781 !rdev->irq.stat_regs.r500.hdmi0_status) { in rs600_irq_process()
785 rdev->irq.stat_regs.r500.disp_int || in rs600_irq_process()
786 rdev->irq.stat_regs.r500.hdmi0_status) { in rs600_irq_process()
789 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in rs600_irq_process()
792 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
793 if (rdev->irq.crtc_vblank_int[0]) { in rs600_irq_process()
794 drm_handle_vblank(rdev->ddev, 0); in rs600_irq_process()
795 rdev->pm.vblank_sync = true; in rs600_irq_process()
796 wake_up(&rdev->irq.vblank_queue); in rs600_irq_process()
798 if (atomic_read(&rdev->irq.pflip[0])) in rs600_irq_process()
799 radeon_crtc_handle_vblank(rdev, 0); in rs600_irq_process()
801 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
802 if (rdev->irq.crtc_vblank_int[1]) { in rs600_irq_process()
803 drm_handle_vblank(rdev->ddev, 1); in rs600_irq_process()
804 rdev->pm.vblank_sync = true; in rs600_irq_process()
805 wake_up(&rdev->irq.vblank_queue); in rs600_irq_process()
807 if (atomic_read(&rdev->irq.pflip[1])) in rs600_irq_process()
808 radeon_crtc_handle_vblank(rdev, 1); in rs600_irq_process()
810 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
814 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
818 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { in rs600_irq_process()
822 status = rs600_irq_ack(rdev); in rs600_irq_process()
825 schedule_delayed_work(&rdev->hotplug_work, 0); in rs600_irq_process()
827 schedule_work(&rdev->audio_work); in rs600_irq_process()
828 if (rdev->msi_enabled) { in rs600_irq_process()
829 switch (rdev->family) { in rs600_irq_process()
845 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) in rs600_get_vblank_counter() argument
853 int rs600_mc_wait_for_idle(struct radeon_device *rdev) in rs600_mc_wait_for_idle() argument
857 for (i = 0; i < rdev->usec_timeout; i++) { in rs600_mc_wait_for_idle()
865 static void rs600_gpu_init(struct radeon_device *rdev) in rs600_gpu_init() argument
867 r420_pipes_init(rdev); in rs600_gpu_init()
869 if (rs600_mc_wait_for_idle(rdev)) in rs600_gpu_init()
870 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_gpu_init()
873 static void rs600_mc_init(struct radeon_device *rdev) in rs600_mc_init() argument
877 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rs600_mc_init()
878 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rs600_mc_init()
879 rdev->mc.vram_is_ddr = true; in rs600_mc_init()
880 rdev->mc.vram_width = 128; in rs600_mc_init()
881 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in rs600_mc_init()
882 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in rs600_mc_init()
883 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rs600_mc_init()
884 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in rs600_mc_init()
887 radeon_vram_location(rdev, &rdev->mc, base); in rs600_mc_init()
888 rdev->mc.gtt_base_align = 0; in rs600_mc_init()
889 radeon_gtt_location(rdev, &rdev->mc); in rs600_mc_init()
890 radeon_update_bandwidth_info(rdev); in rs600_mc_init()
893 void rs600_bandwidth_update(struct radeon_device *rdev) in rs600_bandwidth_update() argument
900 if (!rdev->mode_info.mode_config_initialized) in rs600_bandwidth_update()
903 radeon_update_display_priority(rdev); in rs600_bandwidth_update()
905 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update()
906 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
907 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update()
908 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
910 rs690_line_buffer_adjust(rdev, mode0, mode1); in rs600_bandwidth_update()
912 if (rdev->disp_priority == 2) { in rs600_bandwidth_update()
924 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) in rs600_mc_rreg() argument
929 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs600_mc_rreg()
933 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs600_mc_rreg()
937 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) in rs600_mc_wreg() argument
941 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs600_mc_wreg()
945 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs600_mc_wreg()
948 static void rs600_debugfs(struct radeon_device *rdev) in rs600_debugfs() argument
950 if (r100_debugfs_rbbm_init(rdev)) in rs600_debugfs()
954 void rs600_set_safe_registers(struct radeon_device *rdev) in rs600_set_safe_registers() argument
956 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; in rs600_set_safe_registers()
957 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); in rs600_set_safe_registers()
960 static void rs600_mc_program(struct radeon_device *rdev) in rs600_mc_program() argument
965 rv515_mc_stop(rdev, &save); in rs600_mc_program()
968 if (rs600_mc_wait_for_idle(rdev)) in rs600_mc_program()
969 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_mc_program()
977 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in rs600_mc_program()
978 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); in rs600_mc_program()
980 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rs600_mc_program()
982 rv515_mc_resume(rdev, &save); in rs600_mc_program()
985 static int rs600_startup(struct radeon_device *rdev) in rs600_startup() argument
989 rs600_mc_program(rdev); in rs600_startup()
991 rv515_clock_startup(rdev); in rs600_startup()
993 rs600_gpu_init(rdev); in rs600_startup()
996 r = rs600_gart_enable(rdev); in rs600_startup()
1001 r = radeon_wb_init(rdev); in rs600_startup()
1005 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in rs600_startup()
1007 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in rs600_startup()
1012 if (!rdev->irq.installed) { in rs600_startup()
1013 r = radeon_irq_kms_init(rdev); in rs600_startup()
1018 rs600_irq_set(rdev); in rs600_startup()
1019 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in rs600_startup()
1021 r = r100_cp_init(rdev, 1024 * 1024); in rs600_startup()
1023 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in rs600_startup()
1027 r = radeon_ib_pool_init(rdev); in rs600_startup()
1029 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in rs600_startup()
1033 r = radeon_audio_init(rdev); in rs600_startup()
1035 dev_err(rdev->dev, "failed initializing audio\n"); in rs600_startup()
1042 int rs600_resume(struct radeon_device *rdev) in rs600_resume() argument
1047 rs600_gart_disable(rdev); in rs600_resume()
1049 rv515_clock_startup(rdev); in rs600_resume()
1051 if (radeon_asic_reset(rdev)) { in rs600_resume()
1052 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs600_resume()
1057 atom_asic_init(rdev->mode_info.atom_context); in rs600_resume()
1059 rv515_clock_startup(rdev); in rs600_resume()
1061 radeon_surface_init(rdev); in rs600_resume()
1063 rdev->accel_working = true; in rs600_resume()
1064 r = rs600_startup(rdev); in rs600_resume()
1066 rdev->accel_working = false; in rs600_resume()
1071 int rs600_suspend(struct radeon_device *rdev) in rs600_suspend() argument
1073 radeon_pm_suspend(rdev); in rs600_suspend()
1074 radeon_audio_fini(rdev); in rs600_suspend()
1075 r100_cp_disable(rdev); in rs600_suspend()
1076 radeon_wb_disable(rdev); in rs600_suspend()
1077 rs600_irq_disable(rdev); in rs600_suspend()
1078 rs600_gart_disable(rdev); in rs600_suspend()
1082 void rs600_fini(struct radeon_device *rdev) in rs600_fini() argument
1084 radeon_pm_fini(rdev); in rs600_fini()
1085 radeon_audio_fini(rdev); in rs600_fini()
1086 r100_cp_fini(rdev); in rs600_fini()
1087 radeon_wb_fini(rdev); in rs600_fini()
1088 radeon_ib_pool_fini(rdev); in rs600_fini()
1089 radeon_gem_fini(rdev); in rs600_fini()
1090 rs600_gart_fini(rdev); in rs600_fini()
1091 radeon_irq_kms_fini(rdev); in rs600_fini()
1092 radeon_fence_driver_fini(rdev); in rs600_fini()
1093 radeon_bo_fini(rdev); in rs600_fini()
1094 radeon_atombios_fini(rdev); in rs600_fini()
1095 kfree(rdev->bios); in rs600_fini()
1096 rdev->bios = NULL; in rs600_fini()
1099 int rs600_init(struct radeon_device *rdev) in rs600_init() argument
1104 rv515_vga_render_disable(rdev); in rs600_init()
1106 radeon_scratch_init(rdev); in rs600_init()
1108 radeon_surface_init(rdev); in rs600_init()
1110 r100_restore_sanity(rdev); in rs600_init()
1112 if (!radeon_get_bios(rdev)) { in rs600_init()
1113 if (ASIC_IS_AVIVO(rdev)) in rs600_init()
1116 if (rdev->is_atom_bios) { in rs600_init()
1117 r = radeon_atombios_init(rdev); in rs600_init()
1121 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); in rs600_init()
1125 if (radeon_asic_reset(rdev)) { in rs600_init()
1126 dev_warn(rdev->dev, in rs600_init()
1132 if (radeon_boot_test_post_card(rdev) == false) in rs600_init()
1136 radeon_get_clock_info(rdev->ddev); in rs600_init()
1138 rs600_mc_init(rdev); in rs600_init()
1139 rs600_debugfs(rdev); in rs600_init()
1141 r = radeon_fence_driver_init(rdev); in rs600_init()
1145 r = radeon_bo_init(rdev); in rs600_init()
1148 r = rs600_gart_init(rdev); in rs600_init()
1151 rs600_set_safe_registers(rdev); in rs600_init()
1154 radeon_pm_init(rdev); in rs600_init()
1156 rdev->accel_working = true; in rs600_init()
1157 r = rs600_startup(rdev); in rs600_init()
1160 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in rs600_init()
1161 r100_cp_fini(rdev); in rs600_init()
1162 radeon_wb_fini(rdev); in rs600_init()
1163 radeon_ib_pool_fini(rdev); in rs600_init()
1164 rs600_gart_fini(rdev); in rs600_init()
1165 radeon_irq_kms_fini(rdev); in rs600_init()
1166 rdev->accel_working = false; in rs600_init()