3776 	u32 reset_mask = 0;  in si_gpu_check_soft_reset()  local
3787 		reset_mask |= RADEON_RESET_GFX;  in si_gpu_check_soft_reset()
3791 		reset_mask |= RADEON_RESET_CP;  in si_gpu_check_soft_reset()
3794 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in si_gpu_check_soft_reset()
3799 		reset_mask |= RADEON_RESET_RLC;  in si_gpu_check_soft_reset()
3804 		reset_mask |= RADEON_RESET_DMA;  in si_gpu_check_soft_reset()
3809 		reset_mask |= RADEON_RESET_DMA1;  in si_gpu_check_soft_reset()
3814 		reset_mask |= RADEON_RESET_DMA;  in si_gpu_check_soft_reset()
3817 		reset_mask |= RADEON_RESET_DMA1;  in si_gpu_check_soft_reset()
3823 		reset_mask |= RADEON_RESET_IH;  in si_gpu_check_soft_reset()
3826 		reset_mask |= RADEON_RESET_SEM;  in si_gpu_check_soft_reset()
3829 		reset_mask |= RADEON_RESET_GRBM;  in si_gpu_check_soft_reset()
3832 		reset_mask |= RADEON_RESET_VMC;  in si_gpu_check_soft_reset()
3836 		reset_mask |= RADEON_RESET_MC;  in si_gpu_check_soft_reset()
3839 		reset_mask |= RADEON_RESET_DISPLAY;  in si_gpu_check_soft_reset()
3844 		reset_mask |= RADEON_RESET_VMC;  in si_gpu_check_soft_reset()
3847 	if (reset_mask & RADEON_RESET_MC) {  in si_gpu_check_soft_reset()
3848 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in si_gpu_check_soft_reset()
3849 		reset_mask &= ~RADEON_RESET_MC;  in si_gpu_check_soft_reset()
3852 	return reset_mask;  in si_gpu_check_soft_reset()
3855 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in si_gpu_soft_reset()  argument
3861 	if (reset_mask == 0)  in si_gpu_soft_reset()
3864 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in si_gpu_soft_reset()
3882 	if (reset_mask & RADEON_RESET_DMA) {  in si_gpu_soft_reset()
3888 	if (reset_mask & RADEON_RESET_DMA1) {  in si_gpu_soft_reset()
3902 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {  in si_gpu_soft_reset()
3917 	if (reset_mask & RADEON_RESET_CP) {  in si_gpu_soft_reset()
3923 	if (reset_mask & RADEON_RESET_DMA)  in si_gpu_soft_reset()
3926 	if (reset_mask & RADEON_RESET_DMA1)  in si_gpu_soft_reset()
3929 	if (reset_mask & RADEON_RESET_DISPLAY)  in si_gpu_soft_reset()
3932 	if (reset_mask & RADEON_RESET_RLC)  in si_gpu_soft_reset()
3935 	if (reset_mask & RADEON_RESET_SEM)  in si_gpu_soft_reset()
3938 	if (reset_mask & RADEON_RESET_IH)  in si_gpu_soft_reset()
3941 	if (reset_mask & RADEON_RESET_GRBM)  in si_gpu_soft_reset()
3944 	if (reset_mask & RADEON_RESET_VMC)  in si_gpu_soft_reset()
3947 	if (reset_mask & RADEON_RESET_MC)  in si_gpu_soft_reset()
4089 	u32 reset_mask;  in si_asic_reset()  local
4096 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4098 	if (reset_mask)  in si_asic_reset()
4102 	si_gpu_soft_reset(rdev, reset_mask);  in si_asic_reset()
4104 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4107 	if (reset_mask && radeon_hard_reset)  in si_asic_reset()
4110 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4112 	if (!reset_mask)  in si_asic_reset()
4129 	u32 reset_mask = si_gpu_check_soft_reset(rdev);  in si_gfx_is_lockup()  local
4131 	if (!(reset_mask & (RADEON_RESET_GFX |  in si_gfx_is_lockup()