Lines Matching refs:dpm
1767 struct si_power_info *pi = rdev->pm.dpm.priv; in si_get_pi()
1841 u32 p_limit1 = rdev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1842 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
2132 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2135 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2138 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2139 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2141 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2142 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2143 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
2144 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; in si_calculate_adjusted_tdp_limits()
2166 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2179 rdev->pm.dpm.tdp_adjustment, in si_populate_smc_tdp_limits()
2236 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); in si_populate_smc_tdp_limits_2()
2238 …cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_… in si_populate_smc_tdp_limits_2()
2398 if (rdev->pm.dpm.sq_ramping_threshold == 0) in si_populate_sq_ramping_values()
2420 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2539 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2676 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; in si_initialize_smc_cac_tables()
2703 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; in si_initialize_smc_cac_tables()
2942 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
3008 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3009 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
3017 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in si_apply_state_adjust_rules()
3026 if (rdev->pm.dpm.ac_power) in si_apply_state_adjust_rules()
3027 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
3029 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
3035 if (rdev->pm.dpm.ac_power == false) { in si_apply_state_adjust_rules()
3049 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3051 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3053 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3098 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in si_apply_state_adjust_rules()
3099 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in si_apply_state_adjust_rules()
3100 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3101 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3155 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3158 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3161 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3164 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in si_apply_state_adjust_rules()
3178 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3404 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in si_dpm_force_performance_level()
3428 rdev->pm.dpm.forced_level = level; in si_dpm_force_performance_level()
3649 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in si_program_response_times()
3650 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; in si_program_response_times()
3688 if (rdev->pm.dpm.new_active_crtc_count > 0) in si_program_display_gap()
3693 if (rdev->pm.dpm.new_active_crtc_count > 1) in si_program_display_gap()
3703 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in si_program_display_gap()
3704 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in si_program_display_gap()
3707 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) in si_program_display_gap()
3724 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in si_program_display_gap()
3977 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
3998 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_construct_voltage_tables()
4094 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { in si_populate_smc_voltage_tables()
4156 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in si_get_std_voltage_value()
4157 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { in si_get_std_voltage_value()
4158 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4161 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4163 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4165 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4167 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4170 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4176 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4178 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4180 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4182 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4185 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4191 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4192 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4444 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_initial_state()
4530 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4557 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4698 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in si_init_smc_table()
4720 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in si_init_smc_table()
4723 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { in si_init_smc_table()
4728 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in si_init_smc_table()
4734 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) in si_init_smc_table()
4737 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { in si_init_smc_table()
4739 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; in si_init_smc_table()
5005 (rdev->pm.dpm.new_active_crtc_count <= 2)) { in si_convert_power_level_to_smc()
5070 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_convert_power_level_to_smc()
5160 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { in si_is_state_ulv_compatible()
5162 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { in si_is_state_ulv_compatible()
5164 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) in si_is_state_ulv_compatible()
5322 if (rdev->pm.dpm.new_active_crtc_count == 0) in si_upload_smc_data()
5326 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { in si_upload_smc_data()
5906 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
5908 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5910 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
6002 rdev->pm.dpm.thermal.min_temp = low_temp; in si_thermal_set_temperature_range()
6003 rdev->pm.dpm.thermal.max_temp = high_temp; in si_thermal_set_temperature_range()
6042 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6049 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6053 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in si_thermal_setup_fan_table()
6057 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in si_thermal_setup_fan_table()
6058 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in si_thermal_setup_fan_table()
6060 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in si_thermal_setup_fan_table()
6061 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in si_thermal_setup_fan_table()
6066 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in si_thermal_setup_fan_table()
6067 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in si_thermal_setup_fan_table()
6068 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in si_thermal_setup_fan_table()
6075 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in si_thermal_setup_fan_table()
6085 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in si_thermal_setup_fan_table()
6101 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6198 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6203 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6260 if (rdev->pm.dpm.fan.ucode_fan_control)
6293 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_smc_fan_control()
6325 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_thermal_controller()
6354 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_enable()
6499 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_disable()
6523 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in si_dpm_pre_set_power_state()
6535 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in si_power_control_set_level()
6727 rdev->pm.dpm.boot_ps = rps; in si_parse_pplib_non_clock_info()
6729 rdev->pm.dpm.uvd_ps = rps; in si_parse_pplib_non_clock_info()
6801 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
6802 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
6803 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
6804 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in si_parse_pplib_clock_info()
6840 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in si_parse_power_table()
6843 if (!rdev->pm.dpm.ps) in si_parse_power_table()
6856 kfree(rdev->pm.dpm.ps); in si_parse_power_table()
6859 rdev->pm.dpm.ps[i].ps_priv = ps; in si_parse_power_table()
6860 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in si_parse_power_table()
6875 &rdev->pm.dpm.ps[i], k, in si_parse_power_table()
6881 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in si_parse_power_table()
6886 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in si_parse_power_table()
6893 rdev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
6894 rdev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
6914 rdev->pm.dpm.priv = si_pi; in si_dpm_init()
6960 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in si_dpm_init()
6964 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in si_dpm_init()
6968 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in si_dpm_init()
6969 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in si_dpm_init()
6970 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in si_dpm_init()
6971 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in si_dpm_init()
6972 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in si_dpm_init()
6973 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in si_dpm_init()
6974 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in si_dpm_init()
6975 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in si_dpm_init()
6976 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in si_dpm_init()
6978 if (rdev->pm.dpm.voltage_response_time == 0) in si_dpm_init()
6979 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in si_dpm_init()
6980 if (rdev->pm.dpm.backbias_response_time == 0) in si_dpm_init()
6981 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in si_dpm_init()
7058 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
7059 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
7060 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
7061 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
7062 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in si_dpm_init()
7063 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7064 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in si_dpm_init()
7069 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
7070 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7071 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
7072 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_dpm_init()
7083 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in si_dpm_fini()
7084 kfree(rdev->pm.dpm.ps[i].ps_priv); in si_dpm_fini()
7086 kfree(rdev->pm.dpm.ps); in si_dpm_fini()
7087 kfree(rdev->pm.dpm.priv); in si_dpm_fini()
7088 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in si_dpm_fini()