1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
2969 					struct radeon_ps *rps)  in si_apply_state_adjust_rules()  argument
2971 	struct ni_ps *ps = ni_get_ps(rps);  in si_apply_state_adjust_rules()
3007 	if (rps->vce_active) {  in si_apply_state_adjust_rules()
3008 		rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;  in si_apply_state_adjust_rules()
3009 		rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;  in si_apply_state_adjust_rules()
3010 		si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,  in si_apply_state_adjust_rules()
3013 		rps->evclk = 0;  in si_apply_state_adjust_rules()
3014 		rps->ecclk = 0;  in si_apply_state_adjust_rules()
3021 	if (rps->vclk || rps->dclk) {  in si_apply_state_adjust_rules()
3097 	if (rps->vce_active) {  in si_apply_state_adjust_rules()
3404 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;  in si_dpm_force_performance_level()  local
3405 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_force_performance_level()
6707 					  struct radeon_ps *rps,  in si_parse_pplib_non_clock_info()  argument
6711 	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);  in si_parse_pplib_non_clock_info()
6712 	rps->class = le16_to_cpu(non_clock_info->usClassification);  in si_parse_pplib_non_clock_info()
6713 	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);  in si_parse_pplib_non_clock_info()
6716 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);  in si_parse_pplib_non_clock_info()
6717 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);  in si_parse_pplib_non_clock_info()
6718 	} else if (r600_is_uvd_state(rps->class, rps->class2)) {  in si_parse_pplib_non_clock_info()
6719 		rps->vclk = RV770_DEFAULT_VCLK_FREQ;  in si_parse_pplib_non_clock_info()
6720 		rps->dclk = RV770_DEFAULT_DCLK_FREQ;  in si_parse_pplib_non_clock_info()
6722 		rps->vclk = 0;  in si_parse_pplib_non_clock_info()
6723 		rps->dclk = 0;  in si_parse_pplib_non_clock_info()
6726 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)  in si_parse_pplib_non_clock_info()
6727 		rdev->pm.dpm.boot_ps = rps;  in si_parse_pplib_non_clock_info()
6728 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)  in si_parse_pplib_non_clock_info()
6729 		rdev->pm.dpm.uvd_ps = rps;  in si_parse_pplib_non_clock_info()
6733 				      struct radeon_ps *rps, int index,  in si_parse_pplib_clock_info()  argument
6739 	struct ni_ps *ps = ni_get_ps(rps);  in si_parse_pplib_clock_info()
6765 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {  in si_parse_pplib_clock_info()
6771 	if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&  in si_parse_pplib_clock_info()
6789 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {  in si_parse_pplib_clock_info()
6799 	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==  in si_parse_pplib_clock_info()
7096 	struct radeon_ps *rps = &eg_pi->current_rps;  in si_dpm_debugfs_print_current_performance_level()  local
7097 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_debugfs_print_current_performance_level()
7107 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in si_dpm_debugfs_print_current_performance_level()
7116 	struct radeon_ps *rps = &eg_pi->current_rps;  in si_dpm_get_current_sclk()  local
7117 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_get_current_sclk()
7134 	struct radeon_ps *rps = &eg_pi->current_rps;  in si_dpm_get_current_mclk()  local
7135 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_get_current_mclk()