Lines Matching refs:sor
391 int (*probe)(struct tegra_sor *sor);
392 int (*remove)(struct tegra_sor *sor);
474 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) in tegra_sor_readl() argument
476 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
478 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
483 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
486 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
487 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
490 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) in tegra_sor_set_parent_clock() argument
494 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
496 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
500 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
509 struct tegra_sor *sor; member
524 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_set_parent() local
527 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
540 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
548 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_get_parent() local
552 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
574 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, in tegra_clk_sor_pad_register() argument
581 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); in tegra_clk_sor_pad_register()
585 pad->sor = sor; in tegra_clk_sor_pad_register()
595 clk = devm_clk_register(sor->dev, &pad->hw); in tegra_clk_sor_pad_register()
600 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, in tegra_sor_dp_train_fast() argument
613 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_train_fast()
619 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_train_fast()
625 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_train_fast()
628 tegra_sor_writel(sor, 0, SOR_LVDS); in tegra_sor_dp_train_fast()
630 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
634 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
636 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
639 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
643 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
646 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
648 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); in tegra_sor_dp_train_fast()
659 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
663 err = drm_dp_aux_train(sor->aux, link, pattern); in tegra_sor_dp_train_fast()
667 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
671 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
680 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
684 err = drm_dp_aux_train(sor->aux, link, pattern); in tegra_sor_dp_train_fast()
695 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
699 err = drm_dp_aux_train(sor->aux, link, pattern); in tegra_sor_dp_train_fast()
706 static void tegra_sor_super_update(struct tegra_sor *sor) in tegra_sor_super_update() argument
708 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
709 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); in tegra_sor_super_update()
710 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
713 static void tegra_sor_update(struct tegra_sor *sor) in tegra_sor_update() argument
715 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
716 tegra_sor_writel(sor, 1, SOR_STATE0); in tegra_sor_update()
717 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
720 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_setup_pwm() argument
724 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
727 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
729 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
734 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
739 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
749 static int tegra_sor_attach(struct tegra_sor *sor) in tegra_sor_attach() argument
754 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
757 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
758 tegra_sor_super_update(sor); in tegra_sor_attach()
761 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
763 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
764 tegra_sor_super_update(sor); in tegra_sor_attach()
769 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
779 static int tegra_sor_wakeup(struct tegra_sor *sor) in tegra_sor_wakeup() argument
787 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
799 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_power_up() argument
803 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
805 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
810 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
835 static int tegra_sor_compute_params(struct tegra_sor *sor, in tegra_sor_compute_params() argument
903 static int tegra_sor_compute_config(struct tegra_sor *sor, in tegra_sor_compute_config() argument
932 if (tegra_sor_compute_params(sor, ¶ms, i)) in tegra_sor_compute_config()
951 dev_dbg(sor->dev, in tegra_sor_compute_config()
966 dev_err(sor->dev, in tegra_sor_compute_config()
971 dev_err(sor->dev, "watermark too high, forcing to %u\n", in tegra_sor_compute_config()
989 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, in tegra_sor_compute_config()
995 static void tegra_sor_apply_config(struct tegra_sor *sor, in tegra_sor_apply_config() argument
1000 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1003 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1005 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1022 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1024 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1027 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1029 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1032 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1035 static void tegra_sor_mode_set(struct tegra_sor *sor, in tegra_sor_mode_set() argument
1039 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); in tegra_sor_mode_set()
1043 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1089 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1097 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1104 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1111 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1118 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1121 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1124 static int tegra_sor_detach(struct tegra_sor *sor) in tegra_sor_detach() argument
1129 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1131 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1132 tegra_sor_super_update(sor); in tegra_sor_detach()
1137 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1146 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1148 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1149 tegra_sor_super_update(sor); in tegra_sor_detach()
1152 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1154 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1155 tegra_sor_super_update(sor); in tegra_sor_detach()
1160 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1173 static int tegra_sor_power_down(struct tegra_sor *sor) in tegra_sor_power_down() argument
1178 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1181 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1186 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1197 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_power_down()
1199 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_power_down()
1203 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down()
1206 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down()
1211 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
1216 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
1226 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1228 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1232 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1234 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1236 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1239 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1246 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_crc_wait() argument
1253 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1266 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_crc() local
1267 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_crc()
1279 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1281 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1283 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1285 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1287 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1289 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1291 err = tegra_sor_crc_wait(sor, 100); in tegra_sor_show_crc()
1295 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); in tegra_sor_show_crc()
1296 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1428 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_regs() local
1429 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_regs()
1445 offset, tegra_sor_readl(sor, offset)); in tegra_sor_show_regs()
1464 struct tegra_sor *sor = to_sor(output); in tegra_sor_late_register() local
1467 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_sor_late_register()
1469 if (!sor->debugfs_files) in tegra_sor_late_register()
1473 sor->debugfs_files[i].data = sor; in tegra_sor_late_register()
1475 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor); in tegra_sor_late_register()
1482 kfree(sor->debugfs_files); in tegra_sor_late_register()
1483 sor->debugfs_files = NULL; in tegra_sor_late_register()
1492 struct tegra_sor *sor = to_sor(output); in tegra_sor_early_unregister() local
1494 drm_debugfs_remove_files(sor->debugfs_files, count, in tegra_sor_early_unregister()
1496 kfree(sor->debugfs_files); in tegra_sor_early_unregister()
1497 sor->debugfs_files = NULL; in tegra_sor_early_unregister()
1520 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_detect() local
1522 if (sor->aux) in tegra_sor_connector_detect()
1523 return drm_dp_aux_detect(sor->aux); in tegra_sor_connector_detect()
1557 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_get_modes() local
1560 if (sor->aux) in tegra_sor_connector_get_modes()
1561 drm_dp_aux_enable(sor->aux); in tegra_sor_connector_get_modes()
1565 if (sor->aux) in tegra_sor_connector_get_modes()
1566 drm_dp_aux_disable(sor->aux); in tegra_sor_connector_get_modes()
1591 struct tegra_sor *sor = to_sor(output); in tegra_sor_edp_disable() local
1598 err = tegra_sor_detach(sor); in tegra_sor_edp_disable()
1600 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_edp_disable()
1602 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_edp_disable()
1603 tegra_sor_update(sor); in tegra_sor_edp_disable()
1617 err = tegra_sor_power_down(sor); in tegra_sor_edp_disable()
1619 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_edp_disable()
1621 if (sor->aux) { in tegra_sor_edp_disable()
1622 err = drm_dp_aux_disable(sor->aux); in tegra_sor_edp_disable()
1624 dev_err(sor->dev, "failed to disable DP: %d\n", err); in tegra_sor_edp_disable()
1627 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_edp_disable()
1629 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_edp_disable()
1634 pm_runtime_put(sor->dev); in tegra_sor_edp_disable()
1684 struct tegra_sor *sor = to_sor(output); in tegra_sor_edp_enable() local
1695 pm_runtime_get_sync(sor->dev); in tegra_sor_edp_enable()
1700 err = drm_dp_aux_enable(sor->aux); in tegra_sor_edp_enable()
1702 dev_err(sor->dev, "failed to enable DP: %d\n", err); in tegra_sor_edp_enable()
1704 err = drm_dp_link_probe(sor->aux, &link); in tegra_sor_edp_enable()
1706 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); in tegra_sor_edp_enable()
1711 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_edp_enable()
1713 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_edp_enable()
1718 err = tegra_sor_compute_config(sor, mode, &config, &link); in tegra_sor_edp_enable()
1720 dev_err(sor->dev, "failed to compute configuration: %d\n", err); in tegra_sor_edp_enable()
1722 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1725 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1727 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1729 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1732 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1734 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1738 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1740 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1744 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1747 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_edp_enable()
1750 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1757 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1760 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1767 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1770 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1773 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1776 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1778 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1780 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1782 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1784 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1787 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_edp_enable()
1789 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_edp_enable()
1794 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1796 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1801 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1804 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1806 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1808 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1813 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1815 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1819 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_edp_enable()
1822 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_edp_enable()
1823 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_edp_enable()
1826 err = tegra_sor_set_parent_clock(sor, sor->clk_dp); in tegra_sor_edp_enable()
1828 dev_err(sor->dev, "failed to set parent clock: %d\n", err); in tegra_sor_edp_enable()
1831 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1848 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1850 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1853 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1858 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1861 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1869 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1872 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1874 tegra_sor_apply_config(sor, &config); in tegra_sor_edp_enable()
1877 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1880 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1889 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1892 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1894 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1896 err = drm_dp_link_probe(sor->aux, &link); in tegra_sor_edp_enable()
1898 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); in tegra_sor_edp_enable()
1900 err = drm_dp_link_power_up(sor->aux, &link); in tegra_sor_edp_enable()
1902 dev_err(sor->dev, "failed to power up eDP link: %d\n", err); in tegra_sor_edp_enable()
1904 err = drm_dp_link_configure(sor->aux, &link); in tegra_sor_edp_enable()
1906 dev_err(sor->dev, "failed to configure eDP link: %d\n", err); in tegra_sor_edp_enable()
1911 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1914 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1916 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1923 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1934 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1936 err = tegra_sor_dp_train_fast(sor, &link); in tegra_sor_edp_enable()
1938 dev_err(sor->dev, "DP fast link training failed: %d\n", err); in tegra_sor_edp_enable()
1940 dev_dbg(sor->dev, "fast link training succeeded\n"); in tegra_sor_edp_enable()
1942 err = tegra_sor_power_up(sor, 250); in tegra_sor_edp_enable()
1944 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_edp_enable()
1949 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_edp_enable()
1952 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_edp_enable()
1955 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_edp_enable()
1957 tegra_sor_mode_set(sor, mode, state); in tegra_sor_edp_enable()
1960 err = tegra_sor_setup_pwm(sor, 250); in tegra_sor_edp_enable()
1962 dev_err(sor->dev, "failed to setup PWM: %d\n", err); in tegra_sor_edp_enable()
1964 tegra_sor_update(sor); in tegra_sor_edp_enable()
1972 err = tegra_sor_attach(sor); in tegra_sor_edp_enable()
1974 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_edp_enable()
1976 err = tegra_sor_wakeup(sor); in tegra_sor_edp_enable()
1978 dev_err(sor->dev, "failed to enable DC: %d\n", err); in tegra_sor_edp_enable()
1993 struct tegra_sor *sor = to_sor(output); in tegra_sor_encoder_atomic_check() local
2011 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, in tegra_sor_encoder_atomic_check()
2050 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, in tegra_sor_hdmi_write_infopack() argument
2072 dev_err(sor->dev, "unsupported infoframe type: %02x\n", in tegra_sor_hdmi_write_infopack()
2080 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
2092 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
2097 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
2102 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, in tegra_sor_hdmi_setup_avi_infoframe() argument
2111 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2115 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2118 &sor->output.connector, mode); in tegra_sor_hdmi_setup_avi_infoframe()
2120 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
2126 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
2130 tegra_sor_hdmi_write_infopack(sor, buffer, err); in tegra_sor_hdmi_setup_avi_infoframe()
2133 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2136 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2141 static void tegra_sor_write_eld(struct tegra_sor *sor) in tegra_sor_write_eld() argument
2143 size_t length = drm_eld_size(sor->output.connector.eld), i; in tegra_sor_write_eld()
2146 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], in tegra_sor_write_eld()
2156 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); in tegra_sor_write_eld()
2159 static void tegra_sor_audio_prepare(struct tegra_sor *sor) in tegra_sor_audio_prepare() argument
2163 tegra_sor_write_eld(sor); in tegra_sor_audio_prepare()
2166 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
2169 static void tegra_sor_audio_unprepare(struct tegra_sor *sor) in tegra_sor_audio_unprepare() argument
2171 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_unprepare()
2174 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) in tegra_sor_hdmi_enable_audio_infoframe() argument
2183 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2187 frame.channels = sor->format.channels; in tegra_sor_hdmi_enable_audio_infoframe()
2191 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2195 tegra_sor_hdmi_write_infopack(sor, buffer, err); in tegra_sor_hdmi_enable_audio_infoframe()
2197 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2200 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2205 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) in tegra_sor_hdmi_audio_enable() argument
2209 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_hdmi_audio_enable()
2216 if (sor->format.channels != 2) in tegra_sor_hdmi_audio_enable()
2223 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_hdmi_audio_enable()
2226 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); in tegra_sor_hdmi_audio_enable()
2228 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); in tegra_sor_hdmi_audio_enable()
2233 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2237 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2241 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2245 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2247 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2248 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2249 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); in tegra_sor_hdmi_audio_enable()
2251 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); in tegra_sor_hdmi_audio_enable()
2252 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); in tegra_sor_hdmi_audio_enable()
2254 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); in tegra_sor_hdmi_audio_enable()
2255 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); in tegra_sor_hdmi_audio_enable()
2257 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); in tegra_sor_hdmi_audio_enable()
2258 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); in tegra_sor_hdmi_audio_enable()
2260 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2261 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2262 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); in tegra_sor_hdmi_audio_enable()
2264 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2265 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2266 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); in tegra_sor_hdmi_audio_enable()
2268 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2269 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2270 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); in tegra_sor_hdmi_audio_enable()
2272 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2274 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2276 tegra_sor_hdmi_enable_audio_infoframe(sor); in tegra_sor_hdmi_audio_enable()
2279 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) in tegra_sor_hdmi_disable_audio_infoframe() argument
2283 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2285 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2288 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) in tegra_sor_hdmi_audio_disable() argument
2290 tegra_sor_hdmi_disable_audio_infoframe(sor); in tegra_sor_hdmi_audio_disable()
2294 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) in tegra_sor_hdmi_find_settings() argument
2298 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
2299 if (frequency <= sor->settings[i].frequency) in tegra_sor_hdmi_find_settings()
2300 return &sor->settings[i]; in tegra_sor_hdmi_find_settings()
2305 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) in tegra_sor_hdmi_disable_scrambling() argument
2309 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2312 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2315 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_disable() argument
2317 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_disable()
2322 tegra_sor_hdmi_disable_scrambling(sor); in tegra_sor_hdmi_scdc_disable()
2325 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_stop() argument
2327 if (sor->scdc_enabled) { in tegra_sor_hdmi_scdc_stop()
2328 cancel_delayed_work_sync(&sor->scdc); in tegra_sor_hdmi_scdc_stop()
2329 tegra_sor_hdmi_scdc_disable(sor); in tegra_sor_hdmi_scdc_stop()
2333 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) in tegra_sor_hdmi_enable_scrambling() argument
2337 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2340 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2343 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_enable() argument
2345 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_enable()
2350 tegra_sor_hdmi_enable_scrambling(sor); in tegra_sor_hdmi_scdc_enable()
2355 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); in tegra_sor_hdmi_scdc_work() local
2356 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_work()
2360 tegra_sor_hdmi_scdc_enable(sor); in tegra_sor_hdmi_scdc_work()
2363 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_work()
2366 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_start() argument
2368 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; in tegra_sor_hdmi_scdc_start()
2371 mode = &sor->output.encoder.crtc->state->adjusted_mode; in tegra_sor_hdmi_scdc_start()
2374 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_start()
2375 tegra_sor_hdmi_scdc_enable(sor); in tegra_sor_hdmi_scdc_start()
2376 sor->scdc_enabled = true; in tegra_sor_hdmi_scdc_start()
2384 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_disable() local
2388 tegra_sor_audio_unprepare(sor); in tegra_sor_hdmi_disable()
2389 tegra_sor_hdmi_scdc_stop(sor); in tegra_sor_hdmi_disable()
2391 err = tegra_sor_detach(sor); in tegra_sor_hdmi_disable()
2393 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_hdmi_disable()
2395 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_hdmi_disable()
2396 tegra_sor_update(sor); in tegra_sor_hdmi_disable()
2401 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_disable()
2404 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2410 err = tegra_sor_power_down(sor); in tegra_sor_hdmi_disable()
2412 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_hdmi_disable()
2414 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_hdmi_disable()
2416 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_hdmi_disable()
2418 pm_runtime_put(sor->dev); in tegra_sor_hdmi_disable()
2427 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_enable() local
2439 pm_runtime_get_sync(sor->dev); in tegra_sor_hdmi_enable()
2442 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_hdmi_enable()
2444 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2448 div = clk_get_rate(sor->clk) / 1000000 * 4; in tegra_sor_hdmi_enable()
2450 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_hdmi_enable()
2452 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_hdmi_enable()
2456 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2458 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2462 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2464 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2466 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2469 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2471 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2473 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2477 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2480 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2484 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2487 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2490 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2499 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2502 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2509 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2522 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2527 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2530 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2532 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2537 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2541 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2545 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2546 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2548 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2551 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2556 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2559 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_hdmi_enable()
2560 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2563 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_hdmi_enable()
2565 dev_err(sor->dev, "failed to set parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2569 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_hdmi_enable()
2571 dev_err(sor->dev, "failed to set pad clock: %d\n", err); in tegra_sor_hdmi_enable()
2576 rate = clk_get_rate(sor->clk_parent); in tegra_sor_hdmi_enable()
2583 clk_set_rate(sor->clk, rate); in tegra_sor_hdmi_enable()
2585 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2592 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2599 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2620 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); in tegra_sor_hdmi_enable()
2622 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_enable()
2625 tegra_sor_hdmi_disable_audio_infoframe(sor); in tegra_sor_hdmi_enable()
2628 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2631 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2634 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2636 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2639 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); in tegra_sor_hdmi_enable()
2641 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", in tegra_sor_hdmi_enable()
2646 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2653 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2656 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2662 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2664 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2673 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2679 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2685 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2687 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2691 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2693 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2696 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2699 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2701 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2739 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2742 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2744 err = tegra_sor_power_up(sor, 250); in tegra_sor_hdmi_enable()
2746 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_hdmi_enable()
2749 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2752 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2755 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2758 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2760 tegra_sor_mode_set(sor, mode, state); in tegra_sor_hdmi_enable()
2762 tegra_sor_update(sor); in tegra_sor_hdmi_enable()
2765 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2767 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2769 err = tegra_sor_attach(sor); in tegra_sor_hdmi_enable()
2771 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_hdmi_enable()
2776 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_enable()
2779 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2784 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2787 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2792 err = tegra_sor_wakeup(sor); in tegra_sor_hdmi_enable()
2794 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_hdmi_enable()
2796 tegra_sor_hdmi_scdc_start(sor); in tegra_sor_hdmi_enable()
2797 tegra_sor_audio_prepare(sor); in tegra_sor_hdmi_enable()
2810 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_init() local
2816 if (!sor->aux) { in tegra_sor_init()
2817 if (sor->soc->supports_hdmi) { in tegra_sor_init()
2821 } else if (sor->soc->supports_lvds) { in tegra_sor_init()
2826 if (sor->soc->supports_edp) { in tegra_sor_init()
2830 } else if (sor->soc->supports_dp) { in tegra_sor_init()
2836 sor->output.dev = sor->dev; in tegra_sor_init()
2838 drm_connector_init(drm, &sor->output.connector, in tegra_sor_init()
2841 drm_connector_helper_add(&sor->output.connector, in tegra_sor_init()
2843 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_sor_init()
2845 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, in tegra_sor_init()
2847 drm_encoder_helper_add(&sor->output.encoder, helpers); in tegra_sor_init()
2849 drm_connector_attach_encoder(&sor->output.connector, in tegra_sor_init()
2850 &sor->output.encoder); in tegra_sor_init()
2851 drm_connector_register(&sor->output.connector); in tegra_sor_init()
2853 err = tegra_output_init(drm, &sor->output); in tegra_sor_init()
2859 tegra_output_find_possible_crtcs(&sor->output, drm); in tegra_sor_init()
2861 if (sor->aux) { in tegra_sor_init()
2862 err = drm_dp_aux_attach(sor->aux, &sor->output); in tegra_sor_init()
2864 dev_err(sor->dev, "failed to attach DP: %d\n", err); in tegra_sor_init()
2873 if (sor->rst) { in tegra_sor_init()
2874 err = reset_control_acquire(sor->rst); in tegra_sor_init()
2876 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", in tegra_sor_init()
2881 err = reset_control_assert(sor->rst); in tegra_sor_init()
2883 dev_err(sor->dev, "failed to assert SOR reset: %d\n", in tegra_sor_init()
2889 err = clk_prepare_enable(sor->clk); in tegra_sor_init()
2891 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_init()
2897 if (sor->rst) { in tegra_sor_init()
2898 err = reset_control_deassert(sor->rst); in tegra_sor_init()
2900 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", in tegra_sor_init()
2905 reset_control_release(sor->rst); in tegra_sor_init()
2908 err = clk_prepare_enable(sor->clk_safe); in tegra_sor_init()
2912 err = clk_prepare_enable(sor->clk_dp); in tegra_sor_init()
2922 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_init()
2923 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_init()
2930 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_exit() local
2933 tegra_sor_writel(sor, 0, SOR_INT_MASK); in tegra_sor_exit()
2934 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); in tegra_sor_exit()
2936 tegra_output_exit(&sor->output); in tegra_sor_exit()
2938 if (sor->aux) { in tegra_sor_exit()
2939 err = drm_dp_aux_detach(sor->aux); in tegra_sor_exit()
2941 dev_err(sor->dev, "failed to detach DP: %d\n", err); in tegra_sor_exit()
2946 clk_disable_unprepare(sor->clk_safe); in tegra_sor_exit()
2947 clk_disable_unprepare(sor->clk_dp); in tegra_sor_exit()
2948 clk_disable_unprepare(sor->clk); in tegra_sor_exit()
2962 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) in tegra_sor_hdmi_probe() argument
2966 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); in tegra_sor_hdmi_probe()
2967 if (IS_ERR(sor->avdd_io_supply)) { in tegra_sor_hdmi_probe()
2968 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", in tegra_sor_hdmi_probe()
2969 PTR_ERR(sor->avdd_io_supply)); in tegra_sor_hdmi_probe()
2970 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2973 err = regulator_enable(sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2975 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", in tegra_sor_hdmi_probe()
2980 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); in tegra_sor_hdmi_probe()
2981 if (IS_ERR(sor->vdd_pll_supply)) { in tegra_sor_hdmi_probe()
2982 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", in tegra_sor_hdmi_probe()
2983 PTR_ERR(sor->vdd_pll_supply)); in tegra_sor_hdmi_probe()
2984 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2987 err = regulator_enable(sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2989 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", in tegra_sor_hdmi_probe()
2994 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); in tegra_sor_hdmi_probe()
2995 if (IS_ERR(sor->hdmi_supply)) { in tegra_sor_hdmi_probe()
2996 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", in tegra_sor_hdmi_probe()
2997 PTR_ERR(sor->hdmi_supply)); in tegra_sor_hdmi_probe()
2998 return PTR_ERR(sor->hdmi_supply); in tegra_sor_hdmi_probe()
3001 err = regulator_enable(sor->hdmi_supply); in tegra_sor_hdmi_probe()
3003 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); in tegra_sor_hdmi_probe()
3007 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); in tegra_sor_hdmi_probe()
3012 static int tegra_sor_hdmi_remove(struct tegra_sor *sor) in tegra_sor_hdmi_remove() argument
3014 regulator_disable(sor->hdmi_supply); in tegra_sor_hdmi_remove()
3015 regulator_disable(sor->vdd_pll_supply); in tegra_sor_hdmi_remove()
3016 regulator_disable(sor->avdd_io_supply); in tegra_sor_hdmi_remove()
3183 static int tegra_sor_parse_dt(struct tegra_sor *sor) in tegra_sor_parse_dt() argument
3185 struct device_node *np = sor->dev->of_node; in tegra_sor_parse_dt()
3191 if (sor->soc->has_nvdisplay) { in tegra_sor_parse_dt()
3196 sor->index = value; in tegra_sor_parse_dt()
3202 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; in tegra_sor_parse_dt()
3204 if (sor->soc->supports_edp) in tegra_sor_parse_dt()
3205 sor->index = 0; in tegra_sor_parse_dt()
3207 sor->index = 1; in tegra_sor_parse_dt()
3214 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; in tegra_sor_parse_dt()
3218 sor->xbar_cfg[i] = xbar_cfg[i]; in tegra_sor_parse_dt()
3226 struct tegra_sor *sor = data; in tegra_sor_irq() local
3229 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3230 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()
3233 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()
3240 tegra_hda_parse_format(format, &sor->format); in tegra_sor_irq()
3242 tegra_sor_hdmi_audio_enable(sor); in tegra_sor_irq()
3244 tegra_sor_hdmi_audio_disable(sor); in tegra_sor_irq()
3254 struct tegra_sor *sor; in tegra_sor_probe() local
3258 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); in tegra_sor_probe()
3259 if (!sor) in tegra_sor_probe()
3262 sor->soc = of_device_get_match_data(&pdev->dev); in tegra_sor_probe()
3263 sor->output.dev = sor->dev = &pdev->dev; in tegra_sor_probe()
3265 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, in tegra_sor_probe()
3266 sor->soc->num_settings * in tegra_sor_probe()
3267 sizeof(*sor->settings), in tegra_sor_probe()
3269 if (!sor->settings) in tegra_sor_probe()
3272 sor->num_settings = sor->soc->num_settings; in tegra_sor_probe()
3276 sor->aux = drm_dp_aux_find_by_of_node(np); in tegra_sor_probe()
3279 if (!sor->aux) in tegra_sor_probe()
3283 if (!sor->aux) { in tegra_sor_probe()
3284 if (sor->soc->supports_hdmi) { in tegra_sor_probe()
3285 sor->ops = &tegra_sor_hdmi_ops; in tegra_sor_probe()
3286 sor->pad = TEGRA_IO_PAD_HDMI; in tegra_sor_probe()
3287 } else if (sor->soc->supports_lvds) { in tegra_sor_probe()
3295 if (sor->soc->supports_edp) { in tegra_sor_probe()
3296 sor->ops = &tegra_sor_edp_ops; in tegra_sor_probe()
3297 sor->pad = TEGRA_IO_PAD_LVDS; in tegra_sor_probe()
3298 } else if (sor->soc->supports_dp) { in tegra_sor_probe()
3307 err = tegra_sor_parse_dt(sor); in tegra_sor_probe()
3311 err = tegra_output_probe(&sor->output); in tegra_sor_probe()
3317 if (sor->ops && sor->ops->probe) { in tegra_sor_probe()
3318 err = sor->ops->probe(sor); in tegra_sor_probe()
3321 sor->ops->name, err); in tegra_sor_probe()
3327 sor->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_sor_probe()
3328 if (IS_ERR(sor->regs)) { in tegra_sor_probe()
3329 err = PTR_ERR(sor->regs); in tegra_sor_probe()
3339 sor->irq = err; in tegra_sor_probe()
3341 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, in tegra_sor_probe()
3342 dev_name(sor->dev), sor); in tegra_sor_probe()
3348 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); in tegra_sor_probe()
3349 if (IS_ERR(sor->rst)) { in tegra_sor_probe()
3350 err = PTR_ERR(sor->rst); in tegra_sor_probe()
3364 sor->rst = NULL; in tegra_sor_probe()
3367 sor->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sor_probe()
3368 if (IS_ERR(sor->clk)) { in tegra_sor_probe()
3369 err = PTR_ERR(sor->clk); in tegra_sor_probe()
3374 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { in tegra_sor_probe()
3388 sor->clk_out = devm_clk_get(&pdev->dev, name); in tegra_sor_probe()
3389 if (IS_ERR(sor->clk_out)) { in tegra_sor_probe()
3390 err = PTR_ERR(sor->clk_out); in tegra_sor_probe()
3391 dev_err(sor->dev, "failed to get %s clock: %d\n", in tegra_sor_probe()
3397 sor->clk_out = sor->clk; in tegra_sor_probe()
3400 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_sor_probe()
3401 if (IS_ERR(sor->clk_parent)) { in tegra_sor_probe()
3402 err = PTR_ERR(sor->clk_parent); in tegra_sor_probe()
3407 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); in tegra_sor_probe()
3408 if (IS_ERR(sor->clk_safe)) { in tegra_sor_probe()
3409 err = PTR_ERR(sor->clk_safe); in tegra_sor_probe()
3414 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); in tegra_sor_probe()
3415 if (IS_ERR(sor->clk_dp)) { in tegra_sor_probe()
3416 err = PTR_ERR(sor->clk_dp); in tegra_sor_probe()
3425 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); in tegra_sor_probe()
3426 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3427 if (sor->clk_pad != ERR_PTR(-ENOENT)) { in tegra_sor_probe()
3428 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3437 sor->clk_pad = NULL; in tegra_sor_probe()
3445 err = clk_set_parent(sor->clk_out, sor->clk_safe); in tegra_sor_probe()
3451 platform_set_drvdata(pdev, sor); in tegra_sor_probe()
3458 if (!sor->clk_pad) { in tegra_sor_probe()
3466 sor->clk_pad = tegra_clk_sor_pad_register(sor, in tegra_sor_probe()
3471 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3472 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3478 INIT_LIST_HEAD(&sor->client.list); in tegra_sor_probe()
3479 sor->client.ops = &sor_client_ops; in tegra_sor_probe()
3480 sor->client.dev = &pdev->dev; in tegra_sor_probe()
3482 err = host1x_client_register(&sor->client); in tegra_sor_probe()
3492 if (sor->ops && sor->ops->remove) in tegra_sor_probe()
3493 sor->ops->remove(sor); in tegra_sor_probe()
3495 tegra_output_remove(&sor->output); in tegra_sor_probe()
3501 struct tegra_sor *sor = platform_get_drvdata(pdev); in tegra_sor_remove() local
3506 err = host1x_client_unregister(&sor->client); in tegra_sor_remove()
3513 if (sor->ops && sor->ops->remove) { in tegra_sor_remove()
3514 err = sor->ops->remove(sor); in tegra_sor_remove()
3519 tegra_output_remove(&sor->output); in tegra_sor_remove()
3527 struct tegra_sor *sor = dev_get_drvdata(dev); in tegra_sor_suspend() local
3530 if (sor->rst) { in tegra_sor_suspend()
3531 err = reset_control_assert(sor->rst); in tegra_sor_suspend()
3537 reset_control_release(sor->rst); in tegra_sor_suspend()
3542 clk_disable_unprepare(sor->clk); in tegra_sor_suspend()
3549 struct tegra_sor *sor = dev_get_drvdata(dev); in tegra_sor_resume() local
3552 err = clk_prepare_enable(sor->clk); in tegra_sor_resume()
3560 if (sor->rst) { in tegra_sor_resume()
3561 err = reset_control_acquire(sor->rst); in tegra_sor_resume()
3564 clk_disable_unprepare(sor->clk); in tegra_sor_resume()
3568 err = reset_control_deassert(sor->rst); in tegra_sor_resume()
3571 reset_control_release(sor->rst); in tegra_sor_resume()
3572 clk_disable_unprepare(sor->clk); in tegra_sor_resume()