Lines Matching refs:iommu
55 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
59 ret = clk_enable(iommu->pclk); in __enable_clocks()
63 if (iommu->clk) { in __enable_clocks()
64 ret = clk_enable(iommu->clk); in __enable_clocks()
66 clk_disable(iommu->pclk); in __enable_clocks()
72 static void __disable_clocks(struct msm_iommu_dev *iommu) in __disable_clocks() argument
74 if (iommu->clk) in __disable_clocks()
75 clk_disable(iommu->clk); in __disable_clocks()
76 clk_disable(iommu->pclk); in __disable_clocks()
121 struct msm_iommu_dev *iommu = NULL; in __flush_iotlb() local
125 list_for_each_entry(iommu, &priv->list_attached, dom_node) { in __flush_iotlb()
126 ret = __enable_clocks(iommu); in __flush_iotlb()
130 list_for_each_entry(master, &iommu->ctx_list, list) in __flush_iotlb()
131 SET_CTX_TLBIALL(iommu->base, master->num, 0); in __flush_iotlb()
133 __disable_clocks(iommu); in __flush_iotlb()
143 struct msm_iommu_dev *iommu = NULL; in __flush_iotlb_range() local
148 list_for_each_entry(iommu, &priv->list_attached, dom_node) { in __flush_iotlb_range()
149 ret = __enable_clocks(iommu); in __flush_iotlb_range()
153 list_for_each_entry(master, &iommu->ctx_list, list) { in __flush_iotlb_range()
157 iova |= GET_CONTEXTIDR_ASID(iommu->base, in __flush_iotlb_range()
159 SET_TLBIVA(iommu->base, master->num, iova); in __flush_iotlb_range()
164 __disable_clocks(iommu); in __flush_iotlb_range()
214 static void config_mids(struct msm_iommu_dev *iommu, in config_mids() argument
223 SET_M2VCBR_N(iommu->base, mid, 0); in config_mids()
224 SET_CBACR_N(iommu->base, ctx, 0); in config_mids()
227 SET_VMID(iommu->base, mid, 0); in config_mids()
230 SET_CBNDX(iommu->base, mid, ctx); in config_mids()
233 SET_CBVMID(iommu->base, ctx, 0); in config_mids()
236 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx); in config_mids()
239 SET_NSCFG(iommu->base, mid, 3); in config_mids()
375 struct msm_iommu_dev *iommu, *ret = NULL; in find_iommu_for_dev() local
378 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { in find_iommu_for_dev()
379 master = list_first_entry(&iommu->ctx_list, in find_iommu_for_dev()
383 ret = iommu; in find_iommu_for_dev()
393 struct msm_iommu_dev *iommu; in msm_iommu_add_device() local
398 iommu = find_iommu_for_dev(dev); in msm_iommu_add_device()
401 if (iommu) in msm_iommu_add_device()
402 iommu_device_link(&iommu->iommu, dev); in msm_iommu_add_device()
417 struct msm_iommu_dev *iommu; in msm_iommu_remove_device() local
421 iommu = find_iommu_for_dev(dev); in msm_iommu_remove_device()
424 if (iommu) in msm_iommu_remove_device()
425 iommu_device_unlink(&iommu->iommu, dev); in msm_iommu_remove_device()
434 struct msm_iommu_dev *iommu; in msm_iommu_attach_dev() local
442 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { in msm_iommu_attach_dev()
443 master = list_first_entry(&iommu->ctx_list, in msm_iommu_attach_dev()
447 ret = __enable_clocks(iommu); in msm_iommu_attach_dev()
451 list_for_each_entry(master, &iommu->ctx_list, list) { in msm_iommu_attach_dev()
458 msm_iommu_alloc_ctx(iommu->context_map, in msm_iommu_attach_dev()
459 0, iommu->ncb); in msm_iommu_attach_dev()
464 config_mids(iommu, master); in msm_iommu_attach_dev()
465 __program_context(iommu->base, master->num, in msm_iommu_attach_dev()
468 __disable_clocks(iommu); in msm_iommu_attach_dev()
469 list_add(&iommu->dom_node, &priv->list_attached); in msm_iommu_attach_dev()
484 struct msm_iommu_dev *iommu; in msm_iommu_detach_dev() local
491 list_for_each_entry(iommu, &priv->list_attached, dom_node) { in msm_iommu_detach_dev()
492 ret = __enable_clocks(iommu); in msm_iommu_detach_dev()
496 list_for_each_entry(master, &iommu->ctx_list, list) { in msm_iommu_detach_dev()
497 msm_iommu_free_ctx(iommu->context_map, master->num); in msm_iommu_detach_dev()
498 __reset_context(iommu->base, master->num); in msm_iommu_detach_dev()
500 __disable_clocks(iommu); in msm_iommu_detach_dev()
537 struct msm_iommu_dev *iommu; in msm_iommu_iova_to_phys() local
546 iommu = list_first_entry(&priv->list_attached, in msm_iommu_iova_to_phys()
549 if (list_empty(&iommu->ctx_list)) in msm_iommu_iova_to_phys()
552 master = list_first_entry(&iommu->ctx_list, in msm_iommu_iova_to_phys()
557 ret = __enable_clocks(iommu); in msm_iommu_iova_to_phys()
562 SET_CTX_TLBIALL(iommu->base, master->num, 0); in msm_iommu_iova_to_phys()
563 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA); in msm_iommu_iova_to_phys()
565 par = GET_PAR(iommu->base, master->num); in msm_iommu_iova_to_phys()
568 if (GET_NOFAULT_SS(iommu->base, master->num)) in msm_iommu_iova_to_phys()
573 if (GET_FAULT(iommu->base, master->num)) in msm_iommu_iova_to_phys()
576 __disable_clocks(iommu); in msm_iommu_iova_to_phys()
613 struct msm_iommu_dev **iommu, in insert_iommu_master() argument
616 struct msm_iommu_ctx_dev *master = dev->archdata.iommu; in insert_iommu_master()
619 if (list_empty(&(*iommu)->ctx_list)) { in insert_iommu_master()
622 list_add(&master->list, &(*iommu)->ctx_list); in insert_iommu_master()
623 dev->archdata.iommu = master; in insert_iommu_master()
639 struct msm_iommu_dev *iommu; in qcom_iommu_of_xlate() local
644 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) in qcom_iommu_of_xlate()
645 if (iommu->dev->of_node == spec->np) in qcom_iommu_of_xlate()
648 if (!iommu || iommu->dev->of_node != spec->np) { in qcom_iommu_of_xlate()
653 insert_iommu_master(dev, &iommu, spec); in qcom_iommu_of_xlate()
662 struct msm_iommu_dev *iommu = dev_id; in msm_iommu_fault_handler() local
668 if (!iommu) { in msm_iommu_fault_handler()
674 pr_err("base = %08x\n", (unsigned int)iommu->base); in msm_iommu_fault_handler()
676 ret = __enable_clocks(iommu); in msm_iommu_fault_handler()
680 for (i = 0; i < iommu->ncb; i++) { in msm_iommu_fault_handler()
681 fsr = GET_FSR(iommu->base, i); in msm_iommu_fault_handler()
685 print_ctx_regs(iommu->base, i); in msm_iommu_fault_handler()
686 SET_FSR(iommu->base, i, 0x4000000F); in msm_iommu_fault_handler()
689 __disable_clocks(iommu); in msm_iommu_fault_handler()
722 struct msm_iommu_dev *iommu; in msm_iommu_probe() local
725 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL); in msm_iommu_probe()
726 if (!iommu) in msm_iommu_probe()
729 iommu->dev = &pdev->dev; in msm_iommu_probe()
730 INIT_LIST_HEAD(&iommu->ctx_list); in msm_iommu_probe()
732 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk"); in msm_iommu_probe()
733 if (IS_ERR(iommu->pclk)) { in msm_iommu_probe()
734 dev_err(iommu->dev, "could not get smmu_pclk\n"); in msm_iommu_probe()
735 return PTR_ERR(iommu->pclk); in msm_iommu_probe()
738 ret = clk_prepare(iommu->pclk); in msm_iommu_probe()
740 dev_err(iommu->dev, "could not prepare smmu_pclk\n"); in msm_iommu_probe()
744 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk"); in msm_iommu_probe()
745 if (IS_ERR(iommu->clk)) { in msm_iommu_probe()
746 dev_err(iommu->dev, "could not get iommu_clk\n"); in msm_iommu_probe()
747 clk_unprepare(iommu->pclk); in msm_iommu_probe()
748 return PTR_ERR(iommu->clk); in msm_iommu_probe()
751 ret = clk_prepare(iommu->clk); in msm_iommu_probe()
753 dev_err(iommu->dev, "could not prepare iommu_clk\n"); in msm_iommu_probe()
754 clk_unprepare(iommu->pclk); in msm_iommu_probe()
759 iommu->base = devm_ioremap_resource(iommu->dev, r); in msm_iommu_probe()
760 if (IS_ERR(iommu->base)) { in msm_iommu_probe()
761 dev_err(iommu->dev, "could not get iommu base\n"); in msm_iommu_probe()
762 ret = PTR_ERR(iommu->base); in msm_iommu_probe()
767 iommu->irq = platform_get_irq(pdev, 0); in msm_iommu_probe()
768 if (iommu->irq < 0) { in msm_iommu_probe()
773 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val); in msm_iommu_probe()
775 dev_err(iommu->dev, "could not get ncb\n"); in msm_iommu_probe()
778 iommu->ncb = val; in msm_iommu_probe()
780 msm_iommu_reset(iommu->base, iommu->ncb); in msm_iommu_probe()
781 SET_M(iommu->base, 0, 1); in msm_iommu_probe()
782 SET_PAR(iommu->base, 0, 0); in msm_iommu_probe()
783 SET_V2PCFG(iommu->base, 0, 1); in msm_iommu_probe()
784 SET_V2PPR(iommu->base, 0, 0); in msm_iommu_probe()
785 par = GET_PAR(iommu->base, 0); in msm_iommu_probe()
786 SET_V2PCFG(iommu->base, 0, 0); in msm_iommu_probe()
787 SET_M(iommu->base, 0, 0); in msm_iommu_probe()
795 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL, in msm_iommu_probe()
799 iommu); in msm_iommu_probe()
801 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret); in msm_iommu_probe()
805 list_add(&iommu->dev_node, &qcom_iommu_devices); in msm_iommu_probe()
807 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL, in msm_iommu_probe()
814 iommu_device_set_ops(&iommu->iommu, &msm_iommu_ops); in msm_iommu_probe()
815 iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode); in msm_iommu_probe()
817 ret = iommu_device_register(&iommu->iommu); in msm_iommu_probe()
826 iommu->base, iommu->irq, iommu->ncb); in msm_iommu_probe()
830 clk_unprepare(iommu->clk); in msm_iommu_probe()
831 clk_unprepare(iommu->pclk); in msm_iommu_probe()
842 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev); in msm_iommu_remove() local
844 clk_unprepare(iommu->clk); in msm_iommu_remove()
845 clk_unprepare(iommu->pclk); in msm_iommu_remove()