Lines Matching refs:wb_data
1940 u32 wb_data[2]; in bnx2x_update_pfc_bmac1() local
1951 wb_data[0] = val; in bnx2x_update_pfc_bmac1()
1952 wb_data[1] = 0; in bnx2x_update_pfc_bmac1()
1953 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac1()
1961 wb_data[0] = val; in bnx2x_update_pfc_bmac1()
1962 wb_data[1] = 0; in bnx2x_update_pfc_bmac1()
1963 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac1()
1973 u32 wb_data[2]; in bnx2x_update_pfc_bmac2() local
1984 wb_data[0] = val; in bnx2x_update_pfc_bmac2()
1985 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
1986 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
1995 wb_data[0] = val; in bnx2x_update_pfc_bmac2()
1996 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
1997 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2002 wb_data[0] = 0x0; in bnx2x_update_pfc_bmac2()
2003 wb_data[0] |= (1<<0); /* RX */ in bnx2x_update_pfc_bmac2()
2004 wb_data[0] |= (1<<1); /* TX */ in bnx2x_update_pfc_bmac2()
2005 wb_data[0] |= (1<<2); /* Force initial Xon */ in bnx2x_update_pfc_bmac2()
2006 wb_data[0] |= (1<<3); /* 8 cos */ in bnx2x_update_pfc_bmac2()
2007 wb_data[0] |= (1<<5); /* STATS */ in bnx2x_update_pfc_bmac2()
2008 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
2010 wb_data, 2); in bnx2x_update_pfc_bmac2()
2012 wb_data[0] &= ~(1<<2); in bnx2x_update_pfc_bmac2()
2016 wb_data[0] = 0x8; in bnx2x_update_pfc_bmac2()
2017 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
2020 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2031 wb_data[0] = val; in bnx2x_update_pfc_bmac2()
2032 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
2034 wb_data, 2); in bnx2x_update_pfc_bmac2()
2046 wb_data[0] = val; in bnx2x_update_pfc_bmac2()
2047 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
2048 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2276 u32 wb_data[2]; in bnx2x_bmac1_enable() local
2282 wb_data[0] = 0x3c; in bnx2x_bmac1_enable()
2283 wb_data[1] = 0; in bnx2x_bmac1_enable()
2285 wb_data, 2); in bnx2x_bmac1_enable()
2288 wb_data[0] = ((params->mac_addr[2] << 24) | in bnx2x_bmac1_enable()
2292 wb_data[1] = ((params->mac_addr[0] << 8) | in bnx2x_bmac1_enable()
2294 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); in bnx2x_bmac1_enable()
2302 wb_data[0] = val; in bnx2x_bmac1_enable()
2303 wb_data[1] = 0; in bnx2x_bmac1_enable()
2304 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_bmac1_enable()
2307 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; in bnx2x_bmac1_enable()
2308 wb_data[1] = 0; in bnx2x_bmac1_enable()
2309 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2314 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; in bnx2x_bmac1_enable()
2315 wb_data[1] = 0; in bnx2x_bmac1_enable()
2316 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2319 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; in bnx2x_bmac1_enable()
2320 wb_data[1] = 0; in bnx2x_bmac1_enable()
2321 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2324 wb_data[0] = 0x1000200; in bnx2x_bmac1_enable()
2325 wb_data[1] = 0; in bnx2x_bmac1_enable()
2327 wb_data, 2); in bnx2x_bmac1_enable()
2340 u32 wb_data[2]; in bnx2x_bmac2_enable() local
2344 wb_data[0] = 0; in bnx2x_bmac2_enable()
2345 wb_data[1] = 0; in bnx2x_bmac2_enable()
2346 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_bmac2_enable()
2350 wb_data[0] = 0x3c; in bnx2x_bmac2_enable()
2351 wb_data[1] = 0; in bnx2x_bmac2_enable()
2353 wb_data, 2); in bnx2x_bmac2_enable()
2358 wb_data[0] = ((params->mac_addr[2] << 24) | in bnx2x_bmac2_enable()
2362 wb_data[1] = ((params->mac_addr[0] << 8) | in bnx2x_bmac2_enable()
2365 wb_data, 2); in bnx2x_bmac2_enable()
2370 wb_data[0] = 0x1000200; in bnx2x_bmac2_enable()
2371 wb_data[1] = 0; in bnx2x_bmac2_enable()
2373 wb_data, 2); in bnx2x_bmac2_enable()
2377 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; in bnx2x_bmac2_enable()
2378 wb_data[1] = 0; in bnx2x_bmac2_enable()
2379 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2383 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; in bnx2x_bmac2_enable()
2384 wb_data[1] = 0; in bnx2x_bmac2_enable()
2385 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2388 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD - 2; in bnx2x_bmac2_enable()
2389 wb_data[1] = 0; in bnx2x_bmac2_enable()
2390 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2446 u32 wb_data[2]; in bnx2x_set_bmac_rx() local
2458 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); in bnx2x_set_bmac_rx()
2460 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; in bnx2x_set_bmac_rx()
2462 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; in bnx2x_set_bmac_rx()
2463 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); in bnx2x_set_bmac_rx()
13774 u32 wb_data[2]; in bnx2x_check_half_open_conn() local
13783 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); in bnx2x_check_half_open_conn()
13784 lss_status = (wb_data[0] > 0); in bnx2x_check_half_open_conn()