Lines Matching refs:index
26 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
33 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
38 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
55 pe->index = tid; in mvpp2_prs_init_from_hw()
58 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
69 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
77 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index) in mvpp2_prs_hw_inv() argument
80 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); in mvpp2_prs_hw_inv()
86 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu) in mvpp2_prs_shadow_set() argument
88 priv->prs_shadow[index].valid = true; in mvpp2_prs_shadow_set()
89 priv->prs_shadow[index].lu = lu; in mvpp2_prs_shadow_set()
93 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index, in mvpp2_prs_shadow_ri_set() argument
96 priv->prs_shadow[index].ri_mask = ri_mask; in mvpp2_prs_shadow_ri_set()
97 priv->prs_shadow[index].ri = ri; in mvpp2_prs_shadow_ri_set()
420 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
430 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
467 pe.index = tid; in mvpp2_prs_mac_promisc_set()
487 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
518 pe.index = tid; in mvpp2_prs_dsa_tag_set()
521 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
589 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
602 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
711 pe.index = tid; in mvpp2_prs_vlan_add()
732 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
836 pe.index = tid; in mvpp2_prs_double_vlan_add()
852 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
883 pe.index = tid; in mvpp2_prs_ip4_proto()
907 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
916 pe.index = tid; in mvpp2_prs_ip4_proto()
929 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
948 pe.index = tid; in mvpp2_prs_ip4_cast()
980 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
1004 pe.index = tid; in mvpp2_prs_ip6_proto()
1021 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
1043 pe.index = tid; in mvpp2_prs_ip6_cast()
1061 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1103 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1113 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1125 pe.index = MVPP2_PE_MH_DEFAULT; in mvpp2_prs_mh_init()
1135 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1149 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; in mvpp2_prs_mac_init()
1161 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1208 pe.index = MVPP2_PE_DSA_DEFAULT; in mvpp2_prs_dsa_init()
1213 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_dsa_init()
1232 pe.index = MVPP2_PE_VID_FLTR_DEFAULT; in mvpp2_prs_vid_init()
1250 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1257 pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT; in mvpp2_prs_vid_init()
1276 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1294 pe.index = tid; in mvpp2_prs_etype_init()
1305 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1306 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1307 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1308 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
1320 pe.index = tid; in mvpp2_prs_etype_init()
1335 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1336 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1337 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1338 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
1350 pe.index = tid; in mvpp2_prs_etype_init()
1367 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1368 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1369 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1370 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1384 pe.index = tid; in mvpp2_prs_etype_init()
1404 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1405 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1406 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1407 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
1417 pe.index = tid; in mvpp2_prs_etype_init()
1430 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1431 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1432 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1433 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
1445 pe.index = tid; in mvpp2_prs_etype_init()
1461 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1462 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1463 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1464 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
1471 pe.index = MVPP2_PE_ETH_TYPE_UN; in mvpp2_prs_etype_init()
1487 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1488 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1489 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1490 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
1542 pe.index = MVPP2_PE_VLAN_DBL; in mvpp2_prs_vlan_init()
1557 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1563 pe.index = MVPP2_PE_VLAN_NONE; in mvpp2_prs_vlan_init()
1573 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1593 pe.index = tid; in mvpp2_prs_pppoe_init()
1609 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1618 pe.index = tid; in mvpp2_prs_pppoe_init()
1632 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1643 pe.index = tid; in mvpp2_prs_pppoe_init()
1659 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1670 pe.index = tid; in mvpp2_prs_pppoe_init()
1684 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1728 pe.index = MVPP2_PE_IP4_PROTO_UN; in mvpp2_prs_ip4_init()
1747 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1753 pe.index = MVPP2_PE_IP4_ADDR_UN; in mvpp2_prs_ip4_init()
1767 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1821 pe.index = tid; in mvpp2_prs_ip6_init()
1836 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1842 pe.index = MVPP2_PE_IP6_PROTO_UN; in mvpp2_prs_ip6_init()
1860 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1866 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; in mvpp2_prs_ip6_init()
1880 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1886 pe.index = MVPP2_PE_IP6_ADDR_UN; in mvpp2_prs_ip6_init()
1902 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1974 pe.index = tid; in mvpp2_prs_vid_entry_add()
1998 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_entry_add()
2061 pe.index = tid; in mvpp2_prs_vid_enable_filtering()
2091 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_enable_filtering()
2098 int err, index, i; in mvpp2_prs_default_init() local
2104 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) { in mvpp2_prs_default_init()
2105 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); in mvpp2_prs_default_init()
2109 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index); in mvpp2_prs_default_init()
2115 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) in mvpp2_prs_default_init()
2116 mvpp2_prs_hw_inv(priv, index); in mvpp2_prs_default_init()
2125 for (index = 0; index < MVPP2_MAX_PORTS; index++) in mvpp2_prs_default_init()
2126 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH, in mvpp2_prs_default_init()
2167 int index; in mvpp2_prs_mac_range_equals() local
2169 for (index = 0; index < ETH_ALEN; index++) { in mvpp2_prs_mac_range_equals()
2170 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); in mvpp2_prs_mac_range_equals()
2171 if (tcam_mask != mask[index]) in mvpp2_prs_mac_range_equals()
2174 if ((tcam_mask & tcam_byte) != (da[index] & mask[index])) in mvpp2_prs_mac_range_equals()
2238 pe.index = tid; in mvpp2_prs_mac_da_accept()
2257 mvpp2_prs_hw_inv(priv, pe.index); in mvpp2_prs_mac_da_accept()
2258 priv->prs_shadow[pe.index].valid = false; in mvpp2_prs_mac_da_accept()
2284 mvpp2_prs_shadow_ri_set(priv, pe.index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2292 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
2293 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2325 int index, tid; in mvpp2_prs_mac_del_all() local
2345 for (index = 0; index < ETH_ALEN; index++) in mvpp2_prs_mac_del_all()
2346 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], in mvpp2_prs_mac_del_all()
2347 &da_mask[index]); in mvpp2_prs_mac_del_all()
2425 pe.index = tid; in mvpp2_prs_add_flow()
2438 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_add_flow()
2465 pe.index = tid; in mvpp2_prs_def_flow()
2472 mvpp2_prs_shadow_set(port->priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2484 int mvpp2_prs_hits(struct mvpp2 *priv, int index) in mvpp2_prs_hits() argument
2488 if (index > MVPP2_PRS_TCAM_SRAM_SIZE) in mvpp2_prs_hits()
2491 mvpp2_write(priv, MVPP2_PRS_TCAM_HIT_IDX_REG, index); in mvpp2_prs_hits()