Lines Matching refs:port_base
266 void __iomem *port_base; member
308 static inline void _sc92031_dummy_read(void __iomem *port_base) in _sc92031_dummy_read() argument
310 ioread32(port_base + MAC0); in _sc92031_dummy_read()
313 static u32 _sc92031_mii_wait(void __iomem *port_base) in _sc92031_mii_wait() argument
319 mii_status = ioread32(port_base + Miistatus); in _sc92031_mii_wait()
325 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1) in _sc92031_mii_cmd() argument
327 iowrite32(Mii_Divider, port_base + Miicmd0); in _sc92031_mii_cmd()
329 _sc92031_mii_wait(port_base); in _sc92031_mii_cmd()
331 iowrite32(cmd1, port_base + Miicmd1); in _sc92031_mii_cmd()
332 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0); in _sc92031_mii_cmd()
334 return _sc92031_mii_wait(port_base); in _sc92031_mii_cmd()
337 static void _sc92031_mii_scan(void __iomem *port_base) in _sc92031_mii_scan() argument
339 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6); in _sc92031_mii_scan()
342 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg) in _sc92031_mii_read() argument
344 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13; in _sc92031_mii_read()
347 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val) in _sc92031_mii_write() argument
349 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11)); in _sc92031_mii_write()
355 void __iomem *port_base = priv->port_base; in sc92031_disable_interrupts() local
362 iowrite32(0, port_base + IntrMask); in sc92031_disable_interrupts()
363 _sc92031_dummy_read(port_base); in sc92031_disable_interrupts()
373 void __iomem *port_base = priv->port_base; in sc92031_enable_interrupts() local
380 iowrite32(IntrBits, port_base + IntrMask); in sc92031_enable_interrupts()
386 void __iomem *port_base = priv->port_base; in _sc92031_disable_tx_rx() local
390 iowrite32(priv->rx_config, port_base + RxConfig); in _sc92031_disable_tx_rx()
391 iowrite32(priv->tx_config, port_base + TxConfig); in _sc92031_disable_tx_rx()
397 void __iomem *port_base = priv->port_base; in _sc92031_enable_tx_rx() local
401 iowrite32(priv->rx_config, port_base + RxConfig); in _sc92031_enable_tx_rx()
402 iowrite32(priv->tx_config, port_base + TxConfig); in _sc92031_enable_tx_rx()
419 void __iomem *port_base = priv->port_base; in _sc92031_set_mar() local
450 iowrite32(mar0, port_base + MAR0); in _sc92031_set_mar()
451 iowrite32(mar1, port_base + MAR0 + 4); in _sc92031_set_mar()
457 void __iomem *port_base = priv->port_base; in _sc92031_set_rx_config() local
481 iowrite32(priv->rx_config, port_base + RxConfig); in _sc92031_set_rx_config()
487 void __iomem *port_base = priv->port_base; in _sc92031_check_media() local
490 bmsr = _sc92031_mii_read(port_base, MII_BMSR); in _sc92031_check_media()
495 u16 output_status = _sc92031_mii_read(port_base, in _sc92031_check_media()
497 _sc92031_mii_scan(port_base); in _sc92031_check_media()
526 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig); in _sc92031_check_media()
537 _sc92031_mii_scan(port_base); in _sc92031_check_media()
552 void __iomem *port_base = priv->port_base; in _sc92031_phy_reset() local
555 phy_ctrl = ioread32(port_base + PhyCtrl); in _sc92031_phy_reset()
578 iowrite32(phy_ctrl, port_base + PhyCtrl); in _sc92031_phy_reset()
582 iowrite32(phy_ctrl, port_base + PhyCtrl); in _sc92031_phy_reset()
585 _sc92031_mii_write(port_base, MII_JAB, in _sc92031_phy_reset()
587 _sc92031_mii_scan(port_base); in _sc92031_phy_reset()
596 void __iomem *port_base = priv->port_base; in _sc92031_reset() local
599 iowrite32(0, port_base + PMConfig); in _sc92031_reset()
602 iowrite32(Cfg0_Reset, port_base + Config0); in _sc92031_reset()
605 iowrite32(0, port_base + Config0); in _sc92031_reset()
609 iowrite32(0, port_base + IntrMask); in _sc92031_reset()
612 iowrite32(0, port_base + MAR0); in _sc92031_reset()
613 iowrite32(0, port_base + MAR0 + 4); in _sc92031_reset()
616 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr); in _sc92031_reset()
631 iowrite32(Cfg1_Rcv64K, port_base + Config1); in _sc92031_reset()
640 iowrite32(priv->pm_config, port_base + PMConfig); in _sc92031_reset()
643 ioread32(port_base + IntrStatus); in _sc92031_reset()
649 void __iomem *port_base = priv->port_base; in _sc92031_tx_tasklet() local
658 tx_status = ioread32(port_base + TxStatus0 + entry * 4); in _sc92031_tx_tasklet()
722 void __iomem *port_base = priv->port_base; in _sc92031_rx_tasklet() local
729 rx_ring_head = ioread32(port_base + RxBufWPtr); in _sc92031_rx_tasklet()
819 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr); in _sc92031_rx_tasklet()
836 void __iomem *port_base = priv->port_base; in sc92031_tasklet() local
867 iowrite32(intr_mask, port_base + IntrMask); in sc92031_tasklet()
876 void __iomem *port_base = priv->port_base; in sc92031_interrupt() local
880 iowrite32(0, port_base + IntrMask); in sc92031_interrupt()
881 _sc92031_dummy_read(port_base); in sc92031_interrupt()
883 intr_status = ioread32(port_base + IntrStatus); in sc92031_interrupt()
900 iowrite32(intr_mask, port_base + IntrMask); in sc92031_interrupt()
908 void __iomem *port_base = priv->port_base; in sc92031_get_stats() local
917 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff; in sc92031_get_stats()
935 void __iomem *port_base = priv->port_base; in sc92031_start_xmit() local
975 port_base + TxAddr0 + entry * 4); in sc92031_start_xmit()
976 iowrite32(tx_status, port_base + TxStatus0 + entry * 4); in sc92031_start_xmit()
1121 void __iomem *port_base = priv->port_base; in sc92031_ethtool_get_link_ksettings() local
1129 phy_address = ioread32(port_base + Miicmd1) >> 27; in sc92031_ethtool_get_link_ksettings()
1130 phy_ctrl = ioread32(port_base + PhyCtrl); in sc92031_ethtool_get_link_ksettings()
1132 output_status = _sc92031_mii_read(port_base, MII_OutputStatus); in sc92031_ethtool_get_link_ksettings()
1133 _sc92031_mii_scan(port_base); in sc92031_ethtool_get_link_ksettings()
1184 void __iomem *port_base = priv->port_base; in sc92031_ethtool_set_link_ksettings() local
1242 old_phy_ctrl = ioread32(port_base + PhyCtrl); in sc92031_ethtool_set_link_ksettings()
1246 iowrite32(phy_ctrl, port_base + PhyCtrl); in sc92031_ethtool_set_link_ksettings()
1257 void __iomem *port_base = priv->port_base; in sc92031_ethtool_get_wol() local
1261 pm_config = ioread32(port_base + PMConfig); in sc92031_ethtool_get_wol()
1284 void __iomem *port_base = priv->port_base; in sc92031_ethtool_set_wol() local
1289 pm_config = ioread32(port_base + PMConfig) in sc92031_ethtool_set_wol()
1303 iowrite32(pm_config, port_base + PMConfig); in sc92031_ethtool_set_wol()
1314 void __iomem *port_base = priv->port_base; in sc92031_ethtool_nway_reset() local
1319 bmcr = _sc92031_mii_read(port_base, MII_BMCR); in sc92031_ethtool_nway_reset()
1325 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART); in sc92031_ethtool_nway_reset()
1328 _sc92031_mii_scan(port_base); in sc92031_ethtool_nway_reset()
1399 void __iomem* port_base; in sc92031_probe() local
1422 port_base = pci_iomap(pdev, SC92031_USE_PIO, 0); in sc92031_probe()
1423 if (unlikely(!port_base)) { in sc92031_probe()
1447 priv->port_base = port_base; in sc92031_probe()
1455 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig); in sc92031_probe()
1457 mac0 = ioread32(port_base + MAC0); in sc92031_probe()
1458 mac1 = ioread32(port_base + MAC0 + 4); in sc92031_probe()
1479 pci_iounmap(pdev, port_base); in sc92031_probe()
1493 void __iomem* port_base = priv->port_base; in sc92031_remove() local
1497 pci_iounmap(pdev, port_base); in sc92031_remove()