Lines Matching defs:value
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
36 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
50 u32 value; in dwxgmac2_dma_init_rx_chan() local
66 u32 value; in dwxgmac2_dma_init_tx_chan() local
80 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi() local
142 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode() local
218 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode() local
270 u32 value; in dwxgmac2_dma_start_tx() local
283 u32 value; in dwxgmac2_dma_stop_tx() local
296 u32 value; in dwxgmac2_dma_start_rx() local
309 u32 value; in dwxgmac2_dma_stop_rx() local
460 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso() local
472 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode() local
489 u32 value; in dwxgmac2_set_bfsize() local
499 u32 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph() local