73 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_d0_afe_config_init()
101 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_e0_plus_afe_config_init()
225 	ret = phy_write(dev, location, v);  in phy_set_clr_bits()
243 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);  in bcm7xxx_28nm_ephy_01_afe_config_init()
248 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_01_afe_config_init()
258 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_01_afe_config_init()
314 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
318 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
324 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
328 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
333 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
337 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
343 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
347 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
360 	phy_write(phydev, MII_BMCR,  in bcm7xxx_28nm_ephy_eee_enable()
412 	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);  in bcm7xxx_config_init()
422 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);  in bcm7xxx_config_init()
426 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);  in bcm7xxx_config_init()
428 	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);  in bcm7xxx_config_init()
458 		ret = phy_write(phydev,  in bcm7xxx_suspend()