Lines Matching refs:a1

318 	movel tx_first_bd(%d0), %a1	// A1 = starting TX BD address
325 	movel %d3, (%a1)+		// TX flags + length
326 	movel %d1, (%a1)+		// buffer address
331 	movel %d3, (%a1)+		// Final TX flags + length
332 	movel %d1, (%a1)+		// buffer address
337 	movel #0x90000000, (%a1)+	// RX flags + length
338 	movel %d1, (%a1)+		// buffer address
342 	movel #0xB0000000, (%a1)+	// Final RX flags + length
343 	movel %d1, (%a1)+		// buffer address
346 	movel scc_base_addr(%d0), %a1	// A1 = SCC_BASE address
353 	movew %d1, SCC_TBASE(%a1)	// D1 = offset of first TxBD
355 	movew %d1, SCC_RBASE(%a1)	// D1 = offset of first RxBD
356 	moveb #0x8, SCC_RFCR(%a1)	// Intel mode, 1000
357 	moveb #0x8, SCC_TFCR(%a1)
363 	movel #0xF0B8, SCC_C_MASK(%a1)
364 	movel #0xFFFF, SCC_C_PRES(%a1)
365 	movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
373 	movel #0xDEBB20E3, SCC_C_MASK(%a1)
374 	movel #0xFFFFFFFF, SCC_C_PRES(%a1)
375 	movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
383 	movel #0xF0B8, SCC_C_MASK(%a1)
384 	clrl SCC_C_PRES(%a1)
385 	movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
393 	movel #0xDEBB20E3, SCC_C_MASK(%a1)
394 	clrl SCC_C_PRES(%a1)
395 	movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
401 	movel #0xF0B8, SCC_C_MASK(%a1)
402 	movel #0xFFFF, SCC_C_PRES(%a1)
403 	movew #HDLC_MAX_MRU, SCC_MFLR(%a1) // 0 bytes for CRC
416 	movew #BUFFER_LENGTH, SCC_MRBLR(%a1)
464 	movel 4(%d1), %a1		// A1 = dest address
467 	memcpy_from_pci %a0, %a1, %d2
519 	movel 4(%d2), %a1
520 	tstl %a1
522 	memcpy_to_pci %a0, %a1, %d3
689 	movel %a1, -(%sp)
750 	movel ch_status_addr(%d0), %a1
751 	cmpl STATUS_CABLE(%a1), %d1	// check for change
753 	movel %d1, STATUS_CABLE(%a1)	// update status
762 	movel (%sp)+, %a1