740 	u32 addr, reg_val, mem_val;  in ath10k_hw_qca6174_enable_pll_clock()  local
757 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
762 	if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT)  in ath10k_hw_qca6174_enable_pll_clock()
765 	hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)];  in ath10k_hw_qca6174_enable_pll_clock()
769 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
773 	reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK);  in ath10k_hw_qca6174_enable_pll_clock()
774 	reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) |  in ath10k_hw_qca6174_enable_pll_clock()
776 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
782 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
786 	reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK;  in ath10k_hw_qca6174_enable_pll_clock()
787 	reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME);  in ath10k_hw_qca6174_enable_pll_clock()
788 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
794 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
798 	reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK;  in ath10k_hw_qca6174_enable_pll_clock()
799 	reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV);  in ath10k_hw_qca6174_enable_pll_clock()
800 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
813 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
817 	reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) |  in ath10k_hw_qca6174_enable_pll_clock()
820 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
828 		ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
832 		if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))  in ath10k_hw_qca6174_enable_pll_clock()
840 	if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))  in ath10k_hw_qca6174_enable_pll_clock()
845 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
849 	reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK;  in ath10k_hw_qca6174_enable_pll_clock()
850 	reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS);  in ath10k_hw_qca6174_enable_pll_clock()
851 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
859 		ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
863 		if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))  in ath10k_hw_qca6174_enable_pll_clock()
871 	if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))  in ath10k_hw_qca6174_enable_pll_clock()
876 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
880 	reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK;  in ath10k_hw_qca6174_enable_pll_clock()
881 	reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD);  in ath10k_hw_qca6174_enable_pll_clock()
882 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
888 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);  in ath10k_hw_qca6174_enable_pll_clock()
892 	reg_val &= ~WLAN_PLL_CONTROL_NOPWD_MASK;  in ath10k_hw_qca6174_enable_pll_clock()
893 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);  in ath10k_hw_qca6174_enable_pll_clock()