48 		REG_WRITE(ah, address, bit_position);  in ar9003_mci_wait_for_interrupt()
58 			REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,  in ar9003_mci_wait_for_interrupt()
61 		REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG);  in ar9003_mci_wait_for_interrupt()
234 	REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);  in ar9003_mci_prep_interface()
235 	REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,  in ar9003_mci_prep_interface()
237 	REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,  in ar9003_mci_prep_interface()
272 	REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF);  in ar9003_mci_prep_interface()
273 	REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF);  in ar9003_mci_prep_interface()
274 	REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF);  in ar9003_mci_prep_interface()
275 	REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF);  in ar9003_mci_prep_interface()
276 	REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF);  in ar9003_mci_prep_interface()
284 	REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,  in ar9003_mci_prep_interface()
286 	REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_BT_PRI);  in ar9003_mci_prep_interface()
312 		REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,  in ar9003_mci_prep_interface()
314 		REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,  in ar9003_mci_prep_interface()
318 	REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);  in ar9003_mci_prep_interface()
336 	REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);  in ar9003_mci_disable_interrupt()
337 	REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);  in ar9003_mci_disable_interrupt()
342 	REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT);  in ar9003_mci_enable_interrupt()
343 	REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,  in ar9003_mci_enable_interrupt()
389 		REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);  in ar9003_mci_get_isr()
390 		REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);  in ar9003_mci_get_isr()
469 	REG_WRITE(ah, AR_OBS, 0x4b);  in ar9003_mci_observation_set_up()
753 	REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,  in ar9003_mci_end_reset()
791 	REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);  in ar9003_mci_mute_bt()
792 	REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);  in ar9003_mci_mute_bt()
793 	REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff);  in ar9003_mci_mute_bt()
794 	REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff);  in ar9003_mci_mute_bt()
795 	REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff);  in ar9003_mci_mute_bt()
880 	REG_WRITE(ah, AR_BTCOEX_CTRL, regval);  in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
899 	REG_WRITE(ah, AR_BTCOEX_CTRL, regval);  in ar9003_mci_set_btcoex_ctrl_9565_2ANT()
916 	REG_WRITE(ah, AR_BTCOEX_CTRL, regval);  in ar9003_mci_set_btcoex_ctrl_9462()
935 	REG_WRITE(ah, AR_MCI_GPM_0, mci->gpm_addr);  in ar9003_mci_reset()
936 	REG_WRITE(ah, AR_MCI_GPM_1, mci->gpm_len);  in ar9003_mci_reset()
937 	REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, mci->sched_addr);  in ar9003_mci_reset()
979 			REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), 0x7f7f7f7f);  in ar9003_mci_reset()
989 	REG_WRITE(ah, AR_MCI_COMMAND2, regval);  in ar9003_mci_reset()
994 	REG_WRITE(ah, AR_MCI_COMMAND2, regval);  in ar9003_mci_reset()
1005 	REG_WRITE(ah, AR_MCI_COMMAND2, regval);  in ar9003_mci_reset()
1008 	REG_WRITE(ah, AR_MCI_COMMAND2, regval);  in ar9003_mci_reset()
1013 	REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE,  in ar9003_mci_reset()
1048 		REG_WRITE(ah, AR_BTCOEX_CTRL, 0);  in ar9003_mci_stop_bt()
1151 			REG_WRITE(ah, AR_SELFGEN_MASK, 0x02);  in ar9003_mci_2g5g_switch()
1195 		REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);  in ar9003_mci_send_message()
1199 	REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,  in ar9003_mci_send_message()
1205 			REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i * 4),  in ar9003_mci_send_message()
1209 	REG_WRITE(ah, AR_MCI_COMMAND0,  in ar9003_mci_send_message()
1225 		REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);  in ar9003_mci_send_message()
1285 	REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00);  in ar9003_mci_cleanup()
1435 	REG_WRITE(ah, AR_BTCOEX_CTRL2, (btcoex_ctrl2 | BIT(23)));  in ar9003_mci_set_power_awake()
1443 	REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18)));  in ar9003_mci_set_power_awake()
1447 	REG_WRITE(ah, AR_BTCOEX_CTRL2, btcoex_ctrl2);  in ar9003_mci_set_power_awake()
1448 	REG_WRITE(ah, AR_DIAG_SW, diag_sw);  in ar9003_mci_set_power_awake()
1490 	REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,  in ar9003_mci_get_next_gpm_offset()