287 	struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;  in ath9k_hw_set_4k_power_cal_table()  local
298 	xpdMask = pEepData->modalHeader.xpdGain;  in ath9k_hw_set_4k_power_cal_table()
302 			pEepData->modalHeader.pdGainOverlap;  in ath9k_hw_set_4k_power_cal_table()
307 	pCalBChans = pEepData->calFreqPier2G;  in ath9k_hw_set_4k_power_cal_table()
335 		if (pEepData->baseEepHeader.txMask & (1 << i)) {  in ath9k_hw_set_4k_power_cal_table()
336 			pRawDataset = pEepData->calPierData2G[i];  in ath9k_hw_set_4k_power_cal_table()
395 	 pEepData->ctlIndex[i])						\  in ath9k_hw_set_4k_power_per_rate_table()
397 	    ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))  in ath9k_hw_set_4k_power_per_rate_table()
408 	struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;  in ath9k_hw_set_4k_power_per_rate_table()  local
432 			pEepData->calTargetPowerCck,  in ath9k_hw_set_4k_power_per_rate_table()
436 			pEepData->calTargetPower2G,  in ath9k_hw_set_4k_power_per_rate_table()
440 			pEepData->calTargetPower2GHT20,  in ath9k_hw_set_4k_power_per_rate_table()
447 				pEepData->calTargetPower2GHT40,  in ath9k_hw_set_4k_power_per_rate_table()
451 				pEepData->calTargetPowerCck,  in ath9k_hw_set_4k_power_per_rate_table()
455 				pEepData->calTargetPower2G,  in ath9k_hw_set_4k_power_per_rate_table()
474 			     pEepData->ctlIndex[i]; i++) {  in ath9k_hw_set_4k_power_per_rate_table()
477 				rep = &(pEepData->ctlData[i]);  in ath9k_hw_set_4k_power_per_rate_table()
584 	struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;  in ath9k_hw_4k_set_txpower()  local
585 	struct modal_eep_4k_header *pModal = &pEepData->modalHeader;  in ath9k_hw_4k_set_txpower()