Lines Matching refs:pin_reg
42 u32 pin_reg; in amd_gpio_get_direction() local
46 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_direction()
49 return !(pin_reg & BIT(OUTPUT_ENABLE_OFF)); in amd_gpio_get_direction()
55 u32 pin_reg; in amd_gpio_direction_input() local
59 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()
60 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_input()
61 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_input()
70 u32 pin_reg; in amd_gpio_direction_output() local
75 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_output()
76 pin_reg |= BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_output()
78 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
80 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
81 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_output()
89 u32 pin_reg; in amd_gpio_get_value() local
94 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_value()
97 return !!(pin_reg & BIT(PIN_STS_OFF)); in amd_gpio_get_value()
102 u32 pin_reg; in amd_gpio_set_value() local
107 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_value()
109 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
111 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
112 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_value()
120 u32 pin_reg; in amd_gpio_set_debounce() local
126 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
129 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_set_debounce()
130 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
142 pin_reg |= 1; in amd_gpio_set_debounce()
143 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
144 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
147 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
148 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
149 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
152 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
153 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
154 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
157 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
158 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
159 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
162 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
163 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
164 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
166 pin_reg &= ~DB_CNTRl_MASK; in amd_gpio_set_debounce()
170 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
171 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
172 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
173 pin_reg &= ~DB_CNTRl_MASK; in amd_gpio_set_debounce()
175 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
196 u32 pin_reg; in amd_gpio_dbg_show() local
242 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_dbg_show()
245 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { in amd_gpio_dbg_show()
246 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & in amd_gpio_dbg_show()
254 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && in amd_gpio_dbg_show()
260 if (pin_reg & BIT(LEVEL_TRIG_OFF)) in amd_gpio_dbg_show()
272 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) in amd_gpio_dbg_show()
279 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) in amd_gpio_dbg_show()
284 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) in amd_gpio_dbg_show()
289 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) in amd_gpio_dbg_show()
294 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { in amd_gpio_dbg_show()
296 if (pin_reg & BIT(PULL_UP_SEL_OFF)) in amd_gpio_dbg_show()
305 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) in amd_gpio_dbg_show()
310 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { in amd_gpio_dbg_show()
313 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) in amd_gpio_dbg_show()
321 if (pin_reg & BIT(PIN_STS_OFF)) in amd_gpio_dbg_show()
333 output_value, output_enable, pin_reg); in amd_gpio_dbg_show()
343 u32 pin_reg; in amd_gpio_irq_enable() local
349 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
350 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_enable()
351 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_enable()
352 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
358 u32 pin_reg; in amd_gpio_irq_disable() local
364 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
365 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_disable()
366 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_disable()
367 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
373 u32 pin_reg; in amd_gpio_irq_mask() local
379 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
380 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_mask()
381 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
387 u32 pin_reg; in amd_gpio_irq_unmask() local
393 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
394 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_unmask()
395 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
416 u32 pin_reg, pin_reg_irq_en, mask; in amd_gpio_irq_set_type() local
422 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
435 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
436 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
437 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
438 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_irq_set_type()
443 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
444 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
445 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
446 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_irq_set_type()
451 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
452 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
453 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
454 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_irq_set_type()
459 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
460 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
461 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
462 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_irq_set_type()
463 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; in amd_gpio_irq_set_type()
468 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
469 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
470 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
471 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_irq_set_type()
472 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; in amd_gpio_irq_set_type()
484 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; in amd_gpio_irq_set_type()
501 pin_reg_irq_en = pin_reg; in amd_gpio_irq_set_type()
507 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
645 u32 pin_reg; in amd_pinconf_get() local
652 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_get()
656 arg = pin_reg & DB_TMR_OUT_MASK; in amd_pinconf_get()
660 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); in amd_pinconf_get()
664 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); in amd_pinconf_get()
668 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; in amd_pinconf_get()
688 u32 pin_reg; in amd_pinconf_set() local
697 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_set()
701 pin_reg &= ~DB_TMR_OUT_MASK; in amd_pinconf_set()
702 pin_reg |= arg & DB_TMR_OUT_MASK; in amd_pinconf_set()
706 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); in amd_pinconf_set()
707 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; in amd_pinconf_set()
711 pin_reg &= ~BIT(PULL_UP_SEL_OFF); in amd_pinconf_set()
712 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; in amd_pinconf_set()
713 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); in amd_pinconf_set()
714 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; in amd_pinconf_set()
718 pin_reg &= ~(DRV_STRENGTH_SEL_MASK in amd_pinconf_set()
720 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) in amd_pinconf_set()
730 writel(pin_reg, gpio_dev->base + pin*4); in amd_pinconf_set()