Lines Matching refs:pm8001_cr32
393 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); in pm8001_bar4_shift()
464 value = pm8001_cr32(pm8001_ha, 2, 0xd8); in mpi_set_phys_g3_with_ssc()
536 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); in mpi_init_check()
564 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in check_fw_ready()
565 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in check_fw_ready()
569 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); in check_fw_ready()
576 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); in check_fw_ready()
584 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); in check_fw_ready()
600 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) in check_fw_ready()
602 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) in check_fw_ready()
618 value = pm8001_cr32(pm8001_ha, 0, 0x44); in init_pci_device_addresses()
629 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); in init_pci_device_addresses()
631 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); in init_pci_device_addresses()
633 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); in init_pci_device_addresses()
721 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); in mpi_uninit_check()
765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) in soft_reset_ready_check()
786 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & in soft_reset_ready_check()
789 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in soft_reset_ready_check()
790 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in soft_reset_ready_check()
797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0))); in soft_reset_ready_check()
800 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3))); in soft_reset_ready_check()
840 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); in pm8001_chip_soft_rst()
852 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); in pm8001_chip_soft_rst()
857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); in pm8001_chip_soft_rst()
862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); in pm8001_chip_soft_rst()
867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); in pm8001_chip_soft_rst()
872 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); in pm8001_chip_soft_rst()
878 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) in pm8001_chip_soft_rst()
898 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); in pm8001_chip_soft_rst()
901 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); in pm8001_chip_soft_rst()
916 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); in pm8001_chip_soft_rst()
920 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
928 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); in pm8001_chip_soft_rst()
931 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
939 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); in pm8001_chip_soft_rst()
942 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); in pm8001_chip_soft_rst()
950 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); in pm8001_chip_soft_rst()
962 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); in pm8001_chip_soft_rst()
979 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
998 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
1019 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); in pm8001_chip_soft_rst()
1020 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); in pm8001_chip_soft_rst()
1034 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); in pm8001_chip_soft_rst()
1037 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
1046 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); in pm8001_chip_soft_rst()
1048 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
1053 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); in pm8001_chip_soft_rst()
1055 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); in pm8001_chip_soft_rst()
1060 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); in pm8001_chip_soft_rst()
1071 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
1084 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & in pm8001_chip_soft_rst()
1089 regVal = pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1097 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1101 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1105 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1119 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in pm8001_chip_soft_rst()
1124 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in pm8001_chip_soft_rst()
1131 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1135 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1157 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); in pm8001_hw_chip_rst()
1165 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); in pm8001_hw_chip_rst()
4635 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); in pm8001_chip_is_our_interrupt()
5044 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & in pm8001_get_gsm_dump()
5050 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & in pm8001_get_gsm_dump()