1200 	WRT_REG_DWORD(&reg->ctrl_status,  in qla24xx_unprotect_flash()
1201 	    RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);  in qla24xx_unprotect_flash()
1202 	RD_REG_DWORD(&reg->ctrl_status);	/* PCI Posting. */  in qla24xx_unprotect_flash()
1243 	WRT_REG_DWORD(&reg->ctrl_status,  in qla24xx_protect_flash()
1244 	    RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);  in qla24xx_protect_flash()
1469 	WRT_REG_DWORD(&reg->ctrl_status,  in qla24xx_write_nvram_data()
1470 	    RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);  in qla24xx_write_nvram_data()
1471 	RD_REG_DWORD(&reg->ctrl_status);	/* PCI Posting. */  in qla24xx_write_nvram_data()
1493 	WRT_REG_DWORD(&reg->ctrl_status,  in qla24xx_write_nvram_data()
1494 	    RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);  in qla24xx_write_nvram_data()
1495 	RD_REG_DWORD(&reg->ctrl_status);	/* PCI Posting. */  in qla24xx_write_nvram_data()
1973 	data = RD_REG_WORD(&reg->ctrl_status);  in qla2x00_flash_enable()
1975 	WRT_REG_WORD(&reg->ctrl_status, data);  in qla2x00_flash_enable()
1976 	RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_flash_enable()
1989 	data = RD_REG_WORD(&reg->ctrl_status);  in qla2x00_flash_disable()
1991 	WRT_REG_WORD(&reg->ctrl_status, data);  in qla2x00_flash_disable()
1992 	RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_flash_disable()
2011 	bank_select = RD_REG_WORD(&reg->ctrl_status);  in qla2x00_read_flash_byte()
2019 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_read_flash_byte()
2020 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_read_flash_byte()
2031 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_read_flash_byte()
2032 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_read_flash_byte()
2036 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_read_flash_byte()
2037 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_read_flash_byte()
2071 	bank_select = RD_REG_WORD(&reg->ctrl_status);  in qla2x00_write_flash_byte()
2078 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_write_flash_byte()
2079 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_write_flash_byte()
2082 		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2084 		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2092 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_write_flash_byte()
2093 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_write_flash_byte()
2097 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_write_flash_byte()
2098 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_write_flash_byte()
2107 		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2109 		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2402 	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);  in qla2x00_write_optrom_data()