Lines Matching refs:outb
294 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in mxser_enable_must_enchance_mode()
299 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in mxser_enable_must_enchance_mode()
300 outb(oldlcr, baseio + UART_LCR); in mxser_enable_must_enchance_mode()
310 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in mxser_disable_must_enchance_mode()
315 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in mxser_disable_must_enchance_mode()
316 outb(oldlcr, baseio + UART_LCR); in mxser_disable_must_enchance_mode()
326 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in mxser_set_must_xon1_value()
332 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in mxser_set_must_xon1_value()
333 outb(value, baseio + MOXA_MUST_XON1_REGISTER); in mxser_set_must_xon1_value()
334 outb(oldlcr, baseio + UART_LCR); in mxser_set_must_xon1_value()
343 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in mxser_set_must_xoff1_value()
349 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in mxser_set_must_xoff1_value()
350 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER); in mxser_set_must_xoff1_value()
351 outb(oldlcr, baseio + UART_LCR); in mxser_set_must_xoff1_value()
360 outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR); in mxser_set_must_fifo_value()
366 outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER); in mxser_set_must_fifo_value()
367 outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER); in mxser_set_must_fifo_value()
368 outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER); in mxser_set_must_fifo_value()
369 outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER); in mxser_set_must_fifo_value()
370 outb(oldlcr, info->ioaddr + UART_LCR); in mxser_set_must_fifo_value()
379 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in mxser_set_must_enum_value()
385 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in mxser_set_must_enum_value()
386 outb(value, baseio + MOXA_MUST_ENUM_REGISTER); in mxser_set_must_enum_value()
387 outb(oldlcr, baseio + UART_LCR); in mxser_set_must_enum_value()
397 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in mxser_get_must_hardware_id()
403 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in mxser_get_must_hardware_id()
405 outb(oldlcr, baseio + UART_LCR); in mxser_get_must_hardware_id()
415 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
420 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
421 outb(oldlcr, baseio + UART_LCR); in SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
430 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in mxser_enable_must_tx_software_flow_control()
436 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in mxser_enable_must_tx_software_flow_control()
437 outb(oldlcr, baseio + UART_LCR); in mxser_enable_must_tx_software_flow_control()
446 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in mxser_disable_must_tx_software_flow_control()
451 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in mxser_disable_must_tx_software_flow_control()
452 outb(oldlcr, baseio + UART_LCR); in mxser_disable_must_tx_software_flow_control()
461 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in mxser_enable_must_rx_software_flow_control()
467 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in mxser_enable_must_rx_software_flow_control()
468 outb(oldlcr, baseio + UART_LCR); in mxser_enable_must_rx_software_flow_control()
477 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); in mxser_disable_must_rx_software_flow_control()
482 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); in mxser_disable_must_rx_software_flow_control()
483 outb(oldlcr, baseio + UART_LCR); in mxser_disable_must_rx_software_flow_control()
492 outb(0, io + UART_LCR); in CheckIsMoxaMust()
495 outb(0, io + UART_MCR); in CheckIsMoxaMust()
498 outb(oldmcr, io + UART_MCR); in CheckIsMoxaMust()
560 outb(inb(mp->ioaddr + UART_MCR) | in mxser_dtr_rts()
563 outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS), in mxser_dtr_rts()
604 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_set_baud()
607 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_set_baud()
613 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ in mxser_set_baud()
615 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ in mxser_set_baud()
616 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ in mxser_set_baud()
617 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ in mxser_set_baud()
727 outb(info->IER & ~UART_IER_THRI, in mxser_change_speed()
731 outb(info->IER, info->ioaddr + in mxser_change_speed()
742 outb(info->IER, info->ioaddr + in mxser_change_speed()
749 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_change_speed()
753 outb(info->IER, info->ioaddr + UART_IER); in mxser_change_speed()
804 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */ in mxser_change_speed()
805 outb(cval, info->ioaddr + UART_LCR); in mxser_change_speed()
837 outb(port->IER & ~UART_IER_THRI, in mxser_check_modem_status()
840 outb(port->IER, port->ioaddr + in mxser_check_modem_status()
851 outb(port->IER, port->ioaddr + in mxser_check_modem_status()
884 outb((UART_FCR_CLEAR_RCVR | in mxser_activate()
888 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), in mxser_activate()
916 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ in mxser_activate()
918 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_activate()
927 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ in mxser_activate()
974 outb(0x00, info->ioaddr + UART_IER); in mxser_shutdown_port()
978 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | in mxser_shutdown_port()
982 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, in mxser_shutdown_port()
1028 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), in mxser_flush_buffer()
1030 outb(fcr, info->ioaddr + UART_FCR); in mxser_flush_buffer()
1052 outb(info->IER, info->ioaddr + UART_IER); in mxser_close_port()
1129 outb(info->IER & ~UART_IER_THRI, info->ioaddr + in mxser_write()
1132 outb(info->IER, info->ioaddr + UART_IER); in mxser_write()
1160 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); in mxser_put_char()
1162 outb(info->IER, info->ioaddr + UART_IER); in mxser_put_char()
1182 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); in mxser_flush_chars()
1184 outb(info->IER, info->ioaddr + UART_IER); in mxser_flush_chars()
1387 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_tiocmset()
1396 outb(0, port); in mxser_program_mode()
1397 outb(0, port); in mxser_program_mode()
1398 outb(0, port); in mxser_program_mode()
1401 outb(0, port); in mxser_program_mode()
1431 outb(0xA5, port + 1); in mxser_normal_mode()
1432 outb(0x80, port + 3); in mxser_normal_mode()
1433 outb(12, port + 0); /* 9600 bps */ in mxser_normal_mode()
1434 outb(0, port + 1); in mxser_normal_mode()
1435 outb(0x03, port + 3); /* 8 data bits */ in mxser_normal_mode()
1436 outb(0x13, port + 4); /* loop back mode */ in mxser_normal_mode()
1444 outb(0x00, port + 4); in mxser_normal_mode()
1471 outb(CHIP_CS, port); in mxser_read_register()
1473 outb(CHIP_CS | CHIP_DO, port); in mxser_read_register()
1474 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */ in mxser_read_register()
1476 outb(CHIP_CS, port); in mxser_read_register()
1477 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */ in mxser_read_register()
1483 outb(CHIP_CS, port); in mxser_read_register()
1484 outb(CHIP_CS | CHIP_SK, port); in mxser_read_register()
1489 outb(0, port); in mxser_read_register()
1710 outb(val, info->opmode_ioaddr); in mxser_ioctl()
1856 outb(info->IER, info->ioaddr + UART_IER); in mxser_stoprx()
1859 outb(0, info->ioaddr + UART_IER); in mxser_stoprx()
1861 outb(info->IER, info->ioaddr + UART_IER); in mxser_stoprx()
1867 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_stoprx()
1892 outb(info->IER, info->ioaddr + UART_IER); in mxser_unthrottle()
1895 outb(0, info->ioaddr + UART_IER); in mxser_unthrottle()
1897 outb(info->IER, info->ioaddr + UART_IER); in mxser_unthrottle()
1904 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_unthrottle()
1922 outb(info->IER, info->ioaddr + UART_IER); in mxser_stop()
1934 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); in mxser_start()
1936 outb(info->IER, info->ioaddr + UART_IER); in mxser_start()
2048 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC, in mxser_rs_break()
2051 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC, in mxser_rs_break()
2102 outb(0x23, port->ioaddr + UART_FCR); in mxser_receive_chars()
2164 outb(port->x_char, port->ioaddr + UART_TX); in mxser_transmit_chars()
2181 outb(port->IER, port->ioaddr + UART_IER); in mxser_transmit_chars()
2188 outb(port->port.xmit_buf[port->xmit_tail++], in mxser_transmit_chars()
2205 outb(port->IER, port->ioaddr + UART_IER); in mxser_transmit_chars()
2257 outb(0x27, port->ioaddr + UART_FCR); in mxser_interrupt()
2412 outb(inb(info->ioaddr + UART_IER) & 0xf0, in mxser_initbrd()
2520 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR); in mxser_get_ISA_conf()
2521 outb(0, cap + UART_EFR); /* EFR is the same as FCR */ in mxser_get_ISA_conf()
2522 outb(scratch2, cap + UART_LCR); in mxser_get_ISA_conf()
2523 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR); in mxser_get_ISA_conf()
2632 outb(0, ioaddress + 4); /* default set to RS232 mode */ in mxser_probe()
2633 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */ in mxser_probe()