69 	cr = readb(uap->port.membase + UART010_CR);  in pl010_stop_tx()
80 	cr = readb(uap->port.membase + UART010_CR);  in pl010_start_tx()
91 	cr = readb(uap->port.membase + UART010_CR);  in pl010_stop_rx()
101 	cr = readb(uap->port.membase + UART010_CR);  in pl010_disable_ms()
112 	cr = readb(uap->port.membase + UART010_CR);  in pl010_enable_ms()
121 	status = readb(uap->port.membase + UART01x_FR);  in pl010_rx_chars()
123 		ch = readb(uap->port.membase + UART01x_DR);  in pl010_rx_chars()
132 		rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;  in pl010_rx_chars()
164 		status = readb(uap->port.membase + UART01x_FR);  in pl010_rx_chars()
209 	status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl010_modem_status()
237 	status = readb(uap->port.membase + UART010_IIR);  in pl010_int()
250 			status = readb(uap->port.membase + UART010_IIR);  in pl010_int()
265 	unsigned int status = readb(uap->port.membase + UART01x_FR);  in pl010_tx_empty()
276 	status = readb(uap->port.membase + UART01x_FR);  in pl010_get_mctrl()
304 	lcr_h = readb(uap->port.membase + UART010_LCRH);  in pl010_break_ctl()
338 	uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl010_startup()
370 	writel(readb(uap->port.membase + UART010_LCRH) &  in pl010_shutdown()
456 	old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;  in pl010_set_termios()
575 		status = readb(uap->port.membase + UART01x_FR);  in pl010_console_putchar()
592 	old_cr = readb(uap->port.membase + UART010_CR);  in pl010_console_write()
602 		status = readb(uap->port.membase + UART01x_FR);  in pl010_console_write()
614 	if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {  in pl010_console_get_options()
616 		lcr_h = readb(uap->port.membase + UART010_LCRH);  in pl010_console_get_options()
631 		quot = readb(uap->port.membase + UART010_LCRL) |  in pl010_console_get_options()
632 		       readb(uap->port.membase + UART010_LCRM) << 8;  in pl010_console_get_options()