559 #define MISCSTATUS_TXC_LATCHED		BIT13
580 #define SICR_TXC_ACTIVE			BIT13
582 #define SICR_TXC			(BIT13|BIT12)
1175 		info->cmr_value &= ~BIT13;  in mgsl_isr_receive_status()
1844 	usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));  in shutdown()
4620 				(unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));  in usc_set_sdlc_mode()
4649 			RegValue |= BIT13;  in usc_set_sdlc_mode()
4684 	case HDLC_ENCODING_NRZB:               RegValue |= BIT13; break;  in usc_set_sdlc_mode()
4686 	case HDLC_ENCODING_NRZI_SPACE:	       RegValue |= BIT14 | BIT13; break;  in usc_set_sdlc_mode()
4688 	case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 | BIT13; break;  in usc_set_sdlc_mode()
4690 	case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;  in usc_set_sdlc_mode()
4759 	case HDLC_ENCODING_NRZB:               RegValue |= BIT13; break;  in usc_set_sdlc_mode()
4761 	case HDLC_ENCODING_NRZI_SPACE:         RegValue |= BIT14 | BIT13; break;  in usc_set_sdlc_mode()
4763 	case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 | BIT13; break;  in usc_set_sdlc_mode()
4765 	case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;  in usc_set_sdlc_mode()
5356 		usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );  in usc_process_rxoverrun_sync()
5381 		usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );  in usc_process_rxoverrun_sync()
5411 	usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );  in usc_stop_receiver()
5438 	usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );  in usc_start_receiver()
6804 	 	info->cmr_value |= BIT13;  in mgsl_load_tx_dma_buffer()
6942 	usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );  in mgsl_irq_test()
7510  	info->cmr_value &= ~BIT13;  in usc_loopmode_send_done()
7539 	info->cmr_value |= BIT13;  in usc_loopmode_insert_request()