Lines Matching refs:BIT0
214 …a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
221 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
382 #define MASK_FRAMING BIT0
424 #define IRQ_MASTER BIT0
1847 status = *(p + 1) & (BIT1 + BIT0); in rx_async()
1851 else if (status & BIT0) in rx_async()
1858 else if (status & BIT0) in rx_async()
2071 if (status & BIT0) { in ri_change()
3870 if (!(rd_reg32(info, RDCSR) & BIT0)) in rdma_reset()
3883 if (!(rd_reg32(info, TDCSR) & BIT0)) in tdma_reset()
3991 wr_reg32(info, RDCSR, (BIT2 + BIT0)); in rx_start()
3994 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
4040 wr_reg32(info, TDCSR, BIT2 + BIT0); in tx_start()
4139 val |= BIT0; in async_mode()
4176 val |= BIT0; in async_mode()
4212 val = BIT15 + BIT14 + BIT0; in async_mode()
4301 val |= BIT0; in sync_mode()
4364 val |= BIT0; in sync_mode()
4400 val |= BIT1 + BIT0; in sync_mode()
4448 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); in sync_mode()
4512 if (status & BIT0) in get_signals()
4554 val |= BIT0; in msc_set_vcr()
4676 if (framesize < (2 + crc_size) || status & BIT0) { in rx_get_frame()
4800 if (count && (rd_reg32(info, TDCSR) & BIT0)) in free_tbuf_count()
4843 if (reg_value & BIT0) in tbuf_bytes()