Lines Matching refs:temp
59 u32 temp; in xhci_create_usb3_bos_desc() local
90 temp = readl(&xhci->cap_regs->hcc_params); in xhci_create_usb3_bos_desc()
91 if (HCC_LTC(temp)) in xhci_create_usb3_bos_desc()
96 temp = readl(&xhci->cap_regs->hcs_params3); in xhci_create_usb3_bos_desc()
97 buf[12] = HCS_U1_LATENCY(temp); in xhci_create_usb3_bos_desc()
98 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); in xhci_create_usb3_bos_desc()
163 u16 temp; in xhci_common_hub_descriptor() local
169 temp = 0; in xhci_common_hub_descriptor()
172 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
174 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
177 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
180 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
188 u16 temp; in xhci_usb2_hub_descriptor() local
198 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
199 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
564 u32 temp; in xhci_set_port_power() local
568 temp = readl(port->addr); in xhci_set_port_power()
571 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); in xhci_set_port_power()
573 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
577 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
581 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
585 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
587 if (temp) in xhci_set_port_power()
596 u32 temp; in xhci_port_set_test_mode() local
601 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
602 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
603 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
672 u32 temp; in xhci_set_link_state() local
676 temp = xhci_port_state_to_neutral(portsc); in xhci_set_link_state()
677 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
678 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
679 writel(temp, port->addr); in xhci_set_link_state()
683 portsc, temp); in xhci_set_link_state()
689 u32 temp; in xhci_set_remote_wake_mask() local
691 temp = readl(port->addr); in xhci_set_remote_wake_mask()
692 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
695 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
697 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
700 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
702 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
705 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
707 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
709 writel(temp, port->addr); in xhci_set_remote_wake_mask()
716 u32 temp; in xhci_test_and_clear_bit() local
718 temp = readl(port->addr); in xhci_test_and_clear_bit()
719 if (temp & port_bit) { in xhci_test_and_clear_bit()
720 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
721 temp |= port_bit; in xhci_test_and_clear_bit()
722 writel(temp, port->addr); in xhci_test_and_clear_bit()
1084 u32 temp, status; in xhci_hub_control() local
1135 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1136 if (temp == ~(u32)0) { in xhci_hub_control()
1141 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1142 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1148 hcd->self.busnum, wIndex + 1, temp, status); in xhci_hub_control()
1161 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1178 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1179 if (temp == ~(u32)0) { in xhci_hub_control()
1184 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1188 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1189 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1201 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1202 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1203 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1226 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1230 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1234 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1239 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1242 writel(temp | PORT_PE, ports[wIndex]->addr); in xhci_hub_control()
1243 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1252 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1276 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1286 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1290 if (!(temp & PORT_PE)) { in xhci_hub_control()
1319 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1333 temp = (temp | PORT_RESET); in xhci_hub_control()
1334 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1336 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1337 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); in xhci_hub_control()
1342 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1345 wIndex, temp); in xhci_hub_control()
1348 temp |= PORT_WR; in xhci_hub_control()
1349 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1350 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1355 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1356 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1357 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1358 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1363 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1364 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1365 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1366 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1381 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1387 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1388 if (temp == ~(u32)0) { in xhci_hub_control()
1394 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1397 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1399 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1400 if (temp & PORT_RESET) in xhci_hub_control()
1402 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1403 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1439 ports[wIndex]->addr, temp); in xhci_hub_control()
1443 ports[wIndex]->addr, temp); in xhci_hub_control()
1475 u32 temp, status; in xhci_hub_status_data() local
1505 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1506 if (temp == ~(u32)0) { in xhci_hub_status_data()
1511 trace_xhci_hub_status_data(i, temp); in xhci_hub_status_data()
1513 if ((temp & mask) != 0 || in xhci_hub_status_data()
1520 if ((temp & PORT_RC)) in xhci_hub_status_data()
1688 u32 temp, portsc; in xhci_bus_resume() local
1707 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1708 temp &= ~CMD_EIE; in xhci_bus_resume()
1709 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1785 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1786 temp |= CMD_EIE; in xhci_bus_resume()
1787 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1788 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()