Lines Matching refs:dwidth
809 u32 cycle, u32 dwidth) in tsi148_master_set() argument
949 switch (dwidth) { in tsi148_master_set()
1051 u32 *cycle, u32 *dwidth) in __tsi148_master_get() argument
1092 *dwidth = 0; in __tsi148_master_get()
1151 *dwidth = VME_D16; in __tsi148_master_get()
1153 *dwidth = VME_D32; in __tsi148_master_get()
1161 u32 *cycle, u32 *dwidth) in tsi148_master_get() argument
1168 cycle, dwidth); in tsi148_master_get()
1180 u32 aspace, cycle, dwidth; in tsi148_master_read() local
1193 &cycle, &dwidth); in tsi148_master_read()
1266 u32 aspace, cycle, dwidth; in tsi148_master_write() local
1283 &cycle, &dwidth); in tsi148_master_write()
1420 u32 aspace, u32 cycle, u32 dwidth) in tsi148_dma_set_vme_src_attributes() argument
1462 switch (dwidth) { in tsi148_dma_set_vme_src_attributes()
1520 u32 aspace, u32 cycle, u32 dwidth) in tsi148_dma_set_vme_dest_attributes() argument
1562 switch (dwidth) { in tsi148_dma_set_vme_dest_attributes()
1696 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()
1733 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()