Lines Matching defs:snd_soc_tplg_hw_config
332 struct snd_soc_tplg_hw_config { struct
333 __le32 size; /* in bytes of this structure */
334 __le32 id; /* unique ID - - used to match */
335 __le32 fmt; /* SND_SOC_DAI_FORMAT_ format value */
336 __u8 clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */
337 __u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */
338 __u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
339 __u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
340 __u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
341 __u8 mclk_direction; /* SND_SOC_TPLG_MCLK_ value */
342 __le16 reserved; /* for 32bit alignment */
343 __le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */
344 __le32 bclk_rate; /* BCLK freqency in Hz */
345 __le32 fsync_rate; /* frame clock in Hz */
346 __le32 tdm_slots; /* number of TDM slots in use */
347 __le32 tdm_slot_width; /* width in bits for each slot */
348 __le32 tx_slots; /* bit mask for active Tx slots */
349 __le32 rx_slots; /* bit mask for active Rx slots */
350 __le32 tx_channels; /* number of Tx channels */
351 __le32 tx_chanmap[SND_SOC_TPLG_MAX_CHAN]; /* array of slot number */
352 __le32 rx_channels; /* number of Rx channels */
353 __le32 rx_chanmap[SND_SOC_TPLG_MAX_CHAN]; /* array of slot number */