40 	u32 mask = d->mask;  in irq_gc_mask_disable_reg()  local
43 	irq_reg_writel(gc, mask, ct->regs.disable);  in irq_gc_mask_disable_reg()
44 	*ct->mask_cache &= ~mask;  in irq_gc_mask_disable_reg()
59 	u32 mask = d->mask;  in irq_gc_mask_set_bit()  local
62 	*ct->mask_cache |= mask;  in irq_gc_mask_set_bit()
63 	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);  in irq_gc_mask_set_bit()
79 	u32 mask = d->mask;  in irq_gc_mask_clr_bit()  local
82 	*ct->mask_cache &= ~mask;  in irq_gc_mask_clr_bit()
83 	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);  in irq_gc_mask_clr_bit()
99 	u32 mask = d->mask;  in irq_gc_unmask_enable_reg()  local
102 	irq_reg_writel(gc, mask, ct->regs.enable);  in irq_gc_unmask_enable_reg()
103 	*ct->mask_cache |= mask;  in irq_gc_unmask_enable_reg()
115 	u32 mask = d->mask;  in irq_gc_ack_set_bit()  local
118 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_ack_set_bit()
131 	u32 mask = ~d->mask;  in irq_gc_ack_clr_bit()  local
134 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_ack_clr_bit()
154 	u32 mask = d->mask;  in irq_gc_mask_disable_and_ack_set()  local
157 	irq_reg_writel(gc, mask, ct->regs.disable);  in irq_gc_mask_disable_and_ack_set()
158 	*ct->mask_cache &= ~mask;  in irq_gc_mask_disable_and_ack_set()
159 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_mask_disable_and_ack_set()
171 	u32 mask = d->mask;  in irq_gc_eoi()  local
174 	irq_reg_writel(gc, mask, ct->regs.eoi);  in irq_gc_eoi()
190 	u32 mask = d->mask;  in irq_gc_set_wake()  local
192 	if (!(mask & gc->wake_enabled))  in irq_gc_set_wake()
197 		gc->wake_active |= mask;  in irq_gc_set_wake()
199 		gc->wake_active &= ~mask;  in irq_gc_set_wake()
257 	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;  in irq_gc_init_mask_cache()
263 			mskreg = ct[i].regs.mask;  in irq_gc_init_mask_cache()
420 		data->mask = 1 << idx;  in irq_map_generic_chip()
494 				d->mask = 1 << (i - gc->irq_base);  in irq_setup_generic_chip()