1387 	u32 temp = snd_cs46xx_peek (chip,pcm_channel->pcm_reader_scb->address << 2);  in cs46xx_dsp_pcm_channel_set_period()  local
1388 	temp &= ~DMA_RQ_C1_SOURCE_SIZE_MASK;  in cs46xx_dsp_pcm_channel_set_period()
1392 		temp |= DMA_RQ_C1_SOURCE_MOD1024;  in cs46xx_dsp_pcm_channel_set_period()
1395 		temp |= DMA_RQ_C1_SOURCE_MOD512;  in cs46xx_dsp_pcm_channel_set_period()
1398 		temp |= DMA_RQ_C1_SOURCE_MOD256;  in cs46xx_dsp_pcm_channel_set_period()
1401 		temp |= DMA_RQ_C1_SOURCE_MOD128;  in cs46xx_dsp_pcm_channel_set_period()
1404 		temp |= DMA_RQ_C1_SOURCE_MOD64;  in cs46xx_dsp_pcm_channel_set_period()
1407 		temp |= DMA_RQ_C1_SOURCE_MOD32;  in cs46xx_dsp_pcm_channel_set_period()
1410 		temp |= DMA_RQ_C1_SOURCE_MOD16;  in cs46xx_dsp_pcm_channel_set_period()
1418 	snd_cs46xx_poke (chip,pcm_channel->pcm_reader_scb->address << 2,temp);  in cs46xx_dsp_pcm_channel_set_period()
1426 	u32 temp = snd_cs46xx_peek (chip,WRITEBACK_SCB_ADDR << 2);  in cs46xx_dsp_pcm_ostream_set_period()  local
1427 	temp &= ~DMA_RQ_C1_DEST_SIZE_MASK;  in cs46xx_dsp_pcm_ostream_set_period()
1431 		temp |= DMA_RQ_C1_DEST_MOD1024;  in cs46xx_dsp_pcm_ostream_set_period()
1434 		temp |= DMA_RQ_C1_DEST_MOD512;  in cs46xx_dsp_pcm_ostream_set_period()
1437 		temp |= DMA_RQ_C1_DEST_MOD256;  in cs46xx_dsp_pcm_ostream_set_period()
1440 		temp |= DMA_RQ_C1_DEST_MOD128;  in cs46xx_dsp_pcm_ostream_set_period()
1443 		temp |= DMA_RQ_C1_DEST_MOD64;  in cs46xx_dsp_pcm_ostream_set_period()
1446 		temp |= DMA_RQ_C1_DEST_MOD32;  in cs46xx_dsp_pcm_ostream_set_period()
1449 		temp |= DMA_RQ_C1_DEST_MOD16;  in cs46xx_dsp_pcm_ostream_set_period()
1457 	snd_cs46xx_poke (chip,WRITEBACK_SCB_ADDR << 2,temp);  in cs46xx_dsp_pcm_ostream_set_period()